IP Library Granted Patent US 8,946,702
Granted Patent B2
US 8,946,702 · App. 13/860,792 · Granted Feb 3, 2015

Semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Daisuke Matsubayashi (Atsugi, JP); Keisuke Murayama (Chigaskai, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,946,702
App. No.
13/860,792
Granted
Feb 3, 2015
Kind
B2
Abstract

A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

Claims (53)

1. A semiconductor device comprising:

a first gate electrode layer over an insulating surface;

a first insulating layer over the first gate electrode layer;

oxide semiconductor stacked layers comprising a first oxide semiconductor layer and a second oxide semiconductor layer and overlapping with the first gate electrode layer with the first insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers;

a source electrode layer and a drain electrode layer over and in contact with the second oxide semiconductor layer;

a second insulating layer over and in contact with the source electrode layer, the drain electrode layer, and an upper surface of the second oxide semiconductor layer between the source electrode layer and the drain electrode layer; and

a second gate electrode layer overlapping with the oxide semiconductor stacked layers with the second insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers,

wherein a region of the second oxide semiconductor layer in contact with the second insulating layer has a smaller thickness than a region of the second oxide semiconductor layer in contact with the source electrode layer and a region of the second oxide semiconductor layer in contact with the drain electrode layer.

2. The semiconductor device according to claim 1 ,

wherein the first oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is higher than a gallium content in the first oxide semiconductor layer.

3. The semiconductor device according to claim 1 ,

wherein the second oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is lower than or equal to a gallium content in the second oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein at least one of the first gate electrode layer and the second gate electrode layer is a conductive layer having a work function of 5 eV or more.

5. The semiconductor device according to claim 1 , wherein at least one of the first gate electrode layer and the second gate electrode layer is an In—Ga—Zn—O film comprising nitrogen.

6. A semiconductor device comprising:

a first gate electrode layer over an insulating surface;

a first insulating layer over the first gate electrode layer;

oxide semiconductor stacked layers comprising a first oxide semiconductor layer and a second oxide semiconductor layer and overlapping with the first gate electrode layer with the first insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers;

a source electrode layer and a drain electrode layer over and in contact with the second oxide semiconductor layer;

a second insulating layer over and in contact with the source electrode layer, the drain electrode layer, and an upper surface of the second oxide semiconductor layer between the source electrode layer and the drain electrode layer; and

a second gate electrode layer overlapping with the oxide semiconductor stacked layers with the second insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer have same constituent elements and different compositions of the constituent elements; and

wherein a region of the second oxide semiconductor layer in contact with the second insulating layer has a smaller thickness than a region of the second oxide semiconductor layer in contact with the source electrode layer and a region of the second oxide semiconductor layer in contact with the drain electrode layer.

7. The semiconductor device according to claim 6 ,

wherein the first oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is higher than a gallium content in the first oxide semiconductor layer.

8. The semiconductor device according to claim 6 ,

wherein the second oxide semiconductor layer comprises indium and gallium, and

wherein an indium content is lower than or equal to a gallium content in the second oxide semiconductor layer.

9. The semiconductor device according to claim 6 , wherein at least one of the first gate electrode layer and the second gate electrode layer is a conductive layer having a work function of 5 eV or more.

10. The semiconductor device according to claim 6 , wherein at least one of the first gate electrode layer and the second gate electrode layer is an In—Ga—Zn—O film comprising nitrogen.

11. The semiconductor device according to claim 1 ,

wherein the first oxide semiconductor layer includes a first region and a pair of second regions,

wherein the first region overlaps with the region of the second oxide semiconductor layer,

wherein the pair of second regions overlaps with the source electrode layer and the drain electrode layer, and

wherein a thickness of the first region is substantially the same as thicknesses of the pair of second regions.

12. The semiconductor device according to claim 6 ,

wherein the first oxide semiconductor layer includes a first region and a pair of second regions,

wherein the first region overlaps with the region of the second oxide semiconductor layer,

wherein the pair of second regions overlaps with the source electrode layer and the drain electrode layer, and

wherein a thickness of the first region is substantially the same as thicknesses of the pair of second regions.

13. The semiconductor device according to claim 1 ,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium and gallium,

wherein, in the first oxide semiconductor layer, a concentration of indium is higher than a concentration of gallium, and

wherein, in the second oxide semiconductor layer, a concentration of gallium is higher than a concentration of indium.

14. The semiconductor device according to claim 6 ,

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium and gallium,

wherein, in the first oxide semiconductor layer, a concentration of indium is higher than a concentration of gallium, and

wherein, in the second oxide semiconductor layer, a concentration of gallium is higher than a concentration of indium.

15. The semiconductor device according to claim 1 , wherein a thickness of a portion of the oxide semiconductor stacked layers has a thickness of more than or equal to 3 nm and less than 20 nm, the portion being between the source electrode layer and the drain electrode layer.

16. The semiconductor device according to claim 6 , wherein a thickness of a portion of the oxide semiconductor stacked layers has a thickness of more than or equal to 3 nm and less than 20 nm, the portion being between the source electrode layer and the drain electrode layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2013
From: YAMAZAKI, SHUNPEI; MATSUBAYASHI, DAISUKE; MURAYAMA, KEISUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 030196/0624 →
Priority Claims (1)
JP 2012-091539 · Apr 13, 2012 · national
Continuity (1)
Related Publication 20130270552A1 · Oct 17, 2013