INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY AND METHOD OF MANUFACTURE THEREOF
An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die having an address switch; a bottom electrode contact, free of halogen constituents, characteristic of a chemical vapor deposition or an atomic layer deposition, and coupled to the address switch; a transition material layer directly on the bottom electrode contact; and a top electrode contact, directly on the transition material layer, for forming a non-volatile memory array on the integrated circuit die.
1 . A method of manufacture of an integrated circuit system comprising:
providing an integrated circuit die having an address switch;
forming a bottom electrode contact, free of halogen constituents, having characteristics of a chemical vapor deposition or an atomic layer deposition process, and coupled to the address switch;
depositing a transition material layer directly on the bottom electrode contact; and
depositing a top electrode contact directly on the transition material layer for forming a non-volatile memory array on the integrated circuit die.
2 . The method as claimed in claim 1 wherein forming the bottom electrode contact includes infusing the bottom electrode contact with silicon.
3 . The method as claimed in claim 1 wherein forming the bottom electrode contact includes forming the bottom electrode contact having titanium nitride.
4 . The method as claimed in claim 1 wherein forming the bottom electrode contact includes forming the bottom electrode contact with a precursor of tetrakis-dimethylamino titanium or trischlorodiethylamino titanium.
5 . The method as claimed in claim 1 wherein forming the bottom electrode contact includes forming the bottom electrode contact containing a tungsten free of fluorine.
6 . The method as claimed in claim 1 wherein forming the bottom electrode contact includes forming the bottom electrode contact with an organometallic compound as a precursor with the chemical vapor deposition or the atomic layer deposition process.
7 . A method of manufacture of an integrated circuit system comprising:
providing an integrated circuit die having an address switch;
forming a bottom electrode contact, free of halogen constituents, having characteristics of a chemical vapor deposition or an atomic layer deposition process, and coupled to the address switch;
depositing a transition material layer directly on the bottom electrode contact; and
depositing a top electrode contact, over the integrated circuit die, directly on the transition material layer, for forming a non-volatile memory array on the integrated circuit die.
8 . The method as claimed in claim 7 wherein forming the bottom electrode contact includes forming the bottom electrode contact having a resistivity between one hundred micro-ohm cm to 1 ohm cm.
9 . The method as claimed in claim 7 further comprising:
providing a planar substrate of the integrated circuit die; and
wherein:
forming the bottom electrode contact includes forming the bottom electrode contact on the planar substrate.
10 . The method as claimed in claim 7 further comprising:
forming a narrow trench, of the integrated circuit die, having a width less than one hundred nanometers; and
wherein:
forming the bottom electrode contact includes forming the bottom electrode contact in the narrow trench.
11 . The method as claimed in claim 7 wherein forming the bottom electrode contact includes forming the bottom electrode contact having an amorphous structure or a metallic glass structure.
12 . The method as claimed in claim 7 further comprising:
forming a contact-hole via, of the integrated circuit die, having a diameter less than one hundred nanometers; and
wherein:
forming the bottom electrode contact includes forming the bottom electrode contact in the contact-hole via.
13 . An integrated circuit system comprising:
an integrated circuit die having an address switch;
a bottom electrode contact, free of halogen constituents, characteristic of a chemical vapor deposition or an atomic layer deposition, and coupled to the address switch;
a transition material layer directly on the bottom electrode contact; and
a top electrode contact, directly on the transition material layer, for forming a non-volatile memory array on the integrated circuit die.
14 . The system as claimed in claim 13 further comprising a titanium silicon nitride, having the characteristic of the chemical vapor deposition or the atomic layer deposition, in the bottom electrode contact.
15 . The system as claimed in claim 13 further comprising a tungsten free of the halogen constituents, having the characteristic of the chemical vapor deposition or the atomic layer deposition, in the bottom electrode contact.
16 . The system as claimed in claim 13 wherein the bottom electrode contact has a pre-determined contact depth for determining resistivity of the bottom electrode contact.
17 . The system as claimed in claim 13 wherein the bottom electrode contact has a resistivity between one hundred micro-ohm cm to 1 ohm cm.
18 . The system as claimed in claim 13 wherein the top electrode contact is over the integrated circuit die.
19 . The system as claimed in claim 18 further comprising:
a planar substrate of the integrated circuit die; and
wherein:
the bottom electrode contact is on the planar substrate.
20 . The system as claimed in claim 18 further comprising:
a narrow trench, of the integrated circuit die, having a width less than one hundred nanometers; and
wherein:
the bottom electrode contact is in the narrow trench.
21 . The system as claimed in claim 18 wherein the bottom electrode contact has an amorphous structure or a metallic glass structure.
22 . The system as claimed in claim 18 further comprising:
a contact-hole via, of the integrated circuit die, having a diameter less than one hundred nanometers; and
wherein:
the bottom electrode contact is in the contact-hole via.