Silicon carbide semiconductor device
A silicon carbide substrate includes a first layer of a first conductivity type, a second layer of a second conductivity type provided on the first layer, and a third layer provided on the second layer and doped with an impurity for providing the first conductivity type. The silicon carbide substrate has a trench formed through the third layer and the second layer to reach the first layer. The first layer has a concentration peak of the impurity in a position away from the trench in the first layer. As a result, a silicon carbide semiconductor device having an electric field relaxation structure that can be readily formed is provided.
1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate including a first layer of a first conductivity type, a second layer of a second conductivity type provided on said first layer, and a third layer provided on said second layer and doped with an impurity for providing said first conductivity type, said silicon carbide substrate having a trench formed through said third layer and said second layer to reach said first layer, said first layer having a concentration peak of said impurity in a position away from said trench and along said trench in said first layer;
a gate insulating film covering said trench; and
a gate electrode provided on said gate insulating film, said gate electrode facing a surface of said second layer, with said gate insulating film interposed therebetween,
wherein said second layer has a concentration peak of said impurity in a position away from said trench in said second layer.
2. A silicon carbide semiconductor device comprising:
a silicon carbide substrate including a first layer of a first conductivity type, a second layer of a second conductivity type provided on said first layer, and a third layer provided on said second layer and doped with an impurity for providing said first conductivity type, said silicon carbide substrate having a trench formed through said third layer and said second layer to reach said first layer, said first layer having a concentration peak of said impurity in a position away from said trench and along said trench in said first layer;
a gate insulating film covering said trench; and
a gate electrode provided on said gate insulating film, said gate electrode facing a surface of said second layer, with said gate insulating film interposed therebetween,
wherein the concentration of said impurity in said first layer at the bottom of said trench is not less than a minimum value of the concentration of said impurity in said first layer, and not more than 110% of said minimum value.
3. The silicon carbide semiconductor device according to claim 1 , wherein
at the bottom of said trench, a profile of said concentration peak of said impurity has a dose amount of not less than 1×10 11 /cm 2 .
4. The silicon carbide semiconductor device according to claim 1 , wherein
said silicon carbide substrate is made of silicon carbide having a hexagonal crystal structure of polytype 4H.
5. A silicon carbide semiconductor device comprising:
a silicon carbide substrate including a first layer of a first conductivity type, a second layer of a second conductivity type provided on said first layer, and a third layer provided on said second layer and doped with an impurity for providing said first conductivity type, said silicon carbide substrate having a trench formed through said third layer and said second layer to reach said first layer, said first layer having a concentration peak of said impurity in a position away from said trench and along said trench in said first layer;
a gate insulating film covering said trench; and
a gate electrode provided on said gate insulating film, said gate electrode facing a surface of said second layer, with said gate insulating film interposed therebetween, said second layer has a concentration peak of said impurity in a position away from said trench in said second layer,
wherein said silicon carbide substrate is made of silicon carbide having a hexagonal crystal structure of polytype 4H, and
wherein said surface of said second layer includes a first plane having a plane orientation of {0- 33-8}.
6. The silicon carbide semiconductor device according to claim 5 , wherein
said surface includes said first plane microscopically, and further includes a second plane having a plane orientation of {0-11-1} microscopically.
7. The silicon carbide semiconductor device according to claim 6 , wherein
said first and second planes of said surface form a combined plane having a plane orientation of {0-11-2}.
8. The silicon carbide semiconductor device according to claim 7 , wherein
said surface macroscopically has an off angle of 62°±10° relative to the {000-1} plane.
9. The silicon carbide semiconductor device according to claim 2 , wherein
at the bottom of said trench, a profile of said concentration peak of said impurity has a dose amount of not less than 1×10 11 /cm 2 .