IP Library Granted Patent US 8,854,243
Granted Patent B2
US 8,854,243 · App. 13/869,770 · Granted Oct 7, 2014

AD converter circuit and ad conversion method

Inventors: Masato Yoshioka (Kawasaki, JP); Yanfei Chen (Yokohama, JP); Tatsuya Ide (Kasugai, JP)
Assignees: Fujitsu Limited; Fujitsu Semiconductor Limited
H03M1/38H03M1/468H03M1/54H03M1/145
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Quick Facts
Patent No.
US 8,854,243
App. No.
13/869,770
Granted
Oct 7, 2014
Kind
B2
Abstract

A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.

Claims (24)

1. An analog-to-digital converter circuit configured to convert an analog input signal voltage into a digital signal with a predetermined number of bits, comprising:

a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage between the analog input signal voltage and an analog signal voltage corresponding to the digital signal with the number of higher-order bits;

a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and

an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.

2. The analog-to-digital converter circuit according to claim 1 , comprising an amplifier circuit configured to amplify the residual voltage, wherein

the fixed-quantity change time measurement converter circuit finely converts the residual voltage amplified by the amplifier circuit.

3. The analog-to-digital converter circuit according to claim 1 , wherein

the successive approximation converter circuit performs processing to give one redundant bit to the residual voltage, and

the fixed-quantity change time measurement converter circuit finely converts the residual voltage subjected to the redundancy processing into a digital signal with the number of lower-order bits to which one bit is added.

4. The analog-to-digital converter circuit according to claim 2 , wherein

the successive approximation converter circuit performs processing to give one redundant bit to the residual voltage, and

the fixed-quantity change time measurement converter circuit finely converts the residual voltage subjected to the redundancy processing into a digital signal with the number of lower-order bits to which one bit is added.

5. An analog-to-digital conversion method for converting an analog input signal voltage into a digital signal with a predetermined number of bits, comprising the steps of:

sequentially comparing and coarsely converting the analog input signal voltage into a digital signal with a number of higher-order bits, and also outputting a residual voltage between the analog input signal voltage and an analog signal voltage corresponding to the digital signal with the number of higher-order bits;

finely converting the residual voltage into a digital signal with a number of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and

generating a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits and the digital signal with the number of lower-order bits.

6. The analog-to-digital conversion method according to claim 5 , further comprising amplifying the residual voltage, wherein

the fine converting of the residual voltage finely converts the amplified residual voltage.

7. The analog-to-digital conversion method according to claim 5 , wherein

the coarse converting of the analog input signal voltage performs processing to give one redundant bit to the residual voltage, and

the fine converting of the residual voltage finely converts the residual voltage subjected to the redundancy processing into a digital signal with the number of lower-order bits to which one bit is added.

8. The analog-to-digital conversion method according to claim 6 , wherein

the coarse converting of the analog input signal voltage performs processing to give one redundant bit to the residual, voltage, and

the fine converting of the residual voltage finely converts the amplified residual voltage subjected to the redundancy processing into a digital signal with the number of lower-order bits to which one bit is added.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2018
From: FUJITSU LIMITED
To: SOCIONEXT INC.
Reel/Frame 045562/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035498/0324 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 030309 FRAME 0319. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME TO FUJITSU SEMICONDUCTOR LIMITED. Recorded Sep 4, 2013
From: YOSHIOKA, MASATO; CHEN, YANFEI; IDE, TATSUYA
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 031156/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2013
From: YOSHIOKA, MASATO; CHEN, YANFEI; IDE, TATSUYA
To: FUJITSU LIMITED; FUJITSU SEMICONDUCTOR LIMTED
Reel/Frame 030309/0319 →
Priority Claims (1)
JP 2012-124578 · May 31, 2012 · national
Continuity (1)
Related Publication 20130321189A1 · Dec 5, 2013