Semiconductor Device and Fabricating the Same
A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure having at least one vertex directed toward the area in the substrate.
1 . A semiconductor device comprising:
a substrate;
a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack;
a source structure having at least one vertex directed toward the area in the substrate; and
a drain structure having at least one vertex directed toward the area in the substrate.
2 . The semiconductor device of claim 1 , wherein the source vertex is separated from the drain vertex by a first distance, and wherein the first distance is equal or less than about 30 nm.
3 . The semiconductor device of claim 2 , wherein the gate vertex is away from a line between the source and drain vertexes by a second distance, and wherein the second distance is equal to or less than about 20 nm.
4 . The semiconductor device of claim 1 , wherein the gate vertex has a minimum dimension which is equal or less than 3 nm.
5 . The semiconductor device of claim 1 , wherein the source/drain structure has a material which is different than the substrate.
6 . The semiconductor device of claim 2 , wherein the gate stack includes a high-k dielectric, gate sidewalls, and a metal gate, and has a width greater than 30 nm.
7 . The semiconductor device of claim 1 , wherein the gate vertex has two facets and the two facets have a silicon (111) crystallographic orientation.
8 . The semiconductor device of claim 1 , wherein the source/drain vertex has two facets and the two facets have a silicon (111) crystallographic orientation.
9 . The semiconductor device of claim 1 , wherein the gate stack is formed over a portion of fin.
10 . The semiconductor device of claim 1 , further comprising:
a doped region positioned between the gate vertex, the source vertex and adjacent drain vertex.
11 . A field-effect transistor (FET) comprising:
a substrate;
a high-k/metal gate (HK/MG) stack having a bottom profile with a gate width and a gate vertex extending into the substrate; and
epitaxial source and drain structures disposed on each side of the HK/MG stack, the epitaxial source/drain structures each including a vertex extending towards each other;
wherein a first distance between the source and drain vertexes is less than the gate width; and
wherein a second distance from the gate vertex to a line connecting the source and drain vertexes is less than the first distance.
12 . The FET of claim 11 , wherein the first distance is less than about 30 nm, the second distance is less than about 20 nm, and the gate vertex has a minimum dimension which is equal to or less than 3 nm.
13 . The FET of claim 11 , further comprising:
a doped region positioned between the gate vertex, the source vertex and adjacent drain vertex.
14 . A method comprising:
providing a substrate;
forming a first gate stack over a substrate;
etching portions of the substrate to form a source and a drain recesses such that the gate structure interposes the source and drain recesses, the source and drain recesses including a profile which has at least one source/drain vertex towards the first gate stack and a first distance separating the source vertex and drain vertex;
forming source and drain structures over the recesses;
removing the first gate stack to form a gate trench, which has at least one gate vertex directed towards the source/drain vertexes; and
forming a second gate stack over the gate trench.
15 . The method of claim 14 , wherein each of the source/drain vertexes is formed to have two silicon facets having (111) crystallographic orientations.
16 . The method of claim 14 , wherein the gate vertex is formed to have two silicon facets having (111) crystallographic orientations.
17 . The method of claim 14 , wherein the first distance is equal to or less than about 30 nm.
18 . The method of claim 14 , wherein the second distance is equal to or less than 20 nm.
19 . The method of claim 14 , wherein the gate vertex is formed having a minimum dimension of 3 nm or less.
20 . The method of claim 14 , further comprising:
prior to forming the second gate stack, applying ion-implantation through the gate trench.