High voltage MOS input stage
A differential input stage including two input branches each with a pair of transistors. A bias circuit supplies a separate bias current to each of the input branches. A first transistor of each branch has a first current terminal coupled to a source node receiving a bias current, a second current terminal coupled to an output node, and a control terminal coupled to an input node. A second transistor of each branch has a first current terminal coupled to the corresponding source node, a control terminal coupled to the corresponding input node, and a second current terminal coupled to an intermediate node. The second transistors operate as a current path in higher differential voltage conditions to keep the first transistor active to avoid violating the maximum gate-source voltage.
1. A differential input stage, comprising:
a first input circuit, comprising:
a first transistor having a first current terminal coupled to a first source node, having a second current terminal coupled to a first output node, and having a control terminal coupled to a first input node; and
a second transistor having a first current terminal coupled to said first source node, having a second current terminal coupled to an intermediate node, and having a control terminal coupled to said first input node;
a second input circuit, comprising:
a third transistor having a first current terminal coupled to a second source node, having a second current terminal coupled to a second output node, and having a control terminal coupled to a second input node; and
a fourth transistor having a first current terminal coupled to said second source node, having a second current terminal coupled to said intermediate node, and having a control terminal coupled to said second input node;
a load circuit coupled between said first and second output nodes and a first supply node; and
a bias circuit coupled to said first supply node and a second supply node that develops a first bias current at said first source node and that develops a second bias current to said second source node.
2. The differential input stage of claim 1 , wherein said first, second, third and fourth transistors comprise PMOS transistors.
3. The differential input stage of claim 1 , wherein said first, second, third and fourth transistors comprise NMOS transistors.
4. The differential input stage of claim 1 , wherein said first, second, third and fourth transistors have thin gate oxide.
5. The differential input stage of claim 1 , wherein a W/L ratio of said second and fourth transistors is different than a W/L ratio of said first and third transistors.
6. The differential input stage of claim 1 , wherein said second and fourth transistors are short channel field-effect transistors.
7. The differential input stage of claim 1 , wherein said first and third transistors are matched with each other and wherein said second and fourth transistors are matched with each other.
8. The differential input stage of claim 1 , wherein said load circuit comprises a first resistor coupled between said first output node and said first supply node and a second resistor coupled between said second output node and said first supply node.
9. The differential input stage of claim 1 , wherein said bias circuit comprises:
a fifth transistor having a first current terminal coupled to said second supply node, and having a second current terminal and a control terminal coupled together at a bias node;
a bias current source coupled between said bias node and said first supply node;
a sixth transistor having a first current terminal coupled to said second supply node, having a control terminal coupled to said bias node, and having a second current terminal coupled to said first source node; and
a seventh transistor having a first current terminal coupled to said second supply node, having a control terminal coupled to said bias node, and having a second current terminal coupled to said second source node.
10. The differential input stage of claim 9 , wherein said fifth, sixth and seventh transistors are configured to mirror a bias current generated by said bias current source as a first bias current into said first source node and as a second bias current into said second source node.
11. The differential input stage of claim 10 , wherein said first and second bias currents are substantially equal.
12. An amplifying device, comprising:
a differential input comprising first and second input nodes;
first and second supply nodes; and
a differential input stage coupled to said differential input, comprising:
a first transistor having a first current terminal coupled to a first source node, having a second current terminal coupled to a first output node, and having a control terminal coupled to said first input node;
a second transistor having a first current terminal coupled to said first source node, having a second current terminal coupled to an intermediate node, and having a control terminal coupled to said first input node;
a third transistor having a first current terminal coupled to a second source node, having a second current terminal coupled to a second output node, and having a control terminal coupled to said second input node;
a fourth transistor having a first current terminal coupled to said second source node, having a second current terminal coupled to said intermediate node, and having a control terminal coupled to said second input node;
a load circuit coupled between said first and second output nodes and said first supply node; and
a bias circuit coupled to said first and second supply nodes that develops a first bias current at said first source node and that develops a second bias current to said second source node.
13. The amplifying device of claim 12 , wherein said amplifying device comprises an operational amplifier.
14. The amplifying device of claim 12 , wherein said amplifying device comprises a comparator.
15. The amplifying device of claim 12 , wherein said first, second, third and fourth transistors comprise PMOS transistors.
16. The amplifying device of claim 12 , wherein said first, second, third and fourth transistors comprise NMOS transistors.
17. The amplifying device of claim 12 , wherein said first, second, third and fourth transistors have thin gate oxide.
18. The amplifying device of claim 12 , wherein a W/L ratio of said second and fourth transistors is different than a W/L ratio of said first and third transistors.
19. The amplifying device of claim 12 , wherein said second and fourth transistors are short channel field-effect transistors.
20. The amplifying device of claim 12 , wherein said bias circuit comprises:
a fifth transistor having a first current terminal coupled to said second supply node, and having a second current terminal and a control terminal coupled together at a bias node;
a bias current source coupled between said bias node and said first supply node;
a sixth transistor having a first current terminal coupled to said second supply node, having a control terminal coupled to said bias node, and having a second current terminal coupled to said first source node; and
a seventh transistor having a first current terminal coupled to said second supply node, having a control terminal coupled to said bias node, and having a second current terminal coupled to said second source node.
21. The amplifying device of claim 20 , wherein said fifth, sixth and seventh transistors are configured to mirror a bias current generated by said bias current source as a first bias current into said first source node and as a second bias current into said second source node.
22. The amplifying device of claim 21 , wherein said first and second bias currents are substantially equal.