Semiconductor structure with hard mask disposed on the gate structure
View Patent ↗The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate.
1. A semiconductor structure, comprising:
a substrate;
a first dielectric layer disposed on the substrate;
at least two metal gates disposed in the first dielectric layer;
a spacer disposed on two sides of the metal gate, wherein the spacer has a truncated top surface;
a source/drain region (S/D region) disposed between two metal gates;
a plurality of first contacts disposed in the first dielectric layer that are electrically connected to parts of the S/D region;
a plurality of second contacts disposed in the first dielectric layer that are electrically connected to one of the metal gates, wherein at least one of the first contacts directly connects at least one of the second contacts; and
a hard mask disposed on one of the metal gates, wherein the top surface of the hard mask and the top surface of the first dielectric layer are on the same level.
2. The semiconductor device of claim 1 , further comprising a second dielectric layer disposed on the first dielectric layer.
3. The semiconductor device of claim 2 , further comprising an etching stop layer disposed on two sides of the metal gate, and the etching stop layer has a truncated top surface.
4. The semiconductor device of claim 2 , wherein the first contacts disposed in the first dielectric layer and in the second dielectric layer and each first contact is a monolithically formed structure.
5. The semiconductor device of claim 2 , wherein the second contacts disposed in the first dielectric layer and in the second dielectric layer and each second contact is a monolithically formed structure.
6. The semiconductor device of claim 1 , further comprising at least one fin structure disposed on the substrate.
7. The semiconductor device of claim 1 , further comprising a salicide layer disposed between each S/D region and each first contact.
8. The semiconductor device of claim 3 , further comprising a plurality of third contacts disposed on parts of the first contacts and on parts of the second contacts, wherein each third contact is a monolithically formed structure.
9. The semiconductor device of claim 8 , wherein each third contact comprises a via hole structure and a trace structure, wherein the via hole structure and the trace structure comprise the same material and contact each other directly.