Efficient complex network traffic management in a non-uniform memory system
A network appliance includes a first processor, a second processor, a first storage device, and a second storage device. A first status information is stored in the first storage device. The first processor is coupled to the first storage device. A queue of data is stored in the second storage device. The first status information indicates if traffic data stored in the queue of data is permitted to be transmitted. The second processor is coupled to the second storage device. The first processor communicates with the second processor. The traffic data includes packet information. The first storage device is a high speed memory only accessible to the first processor. The second storage device is a high capacity memory accessible to multiple processors. The first status information is a permitted bit that indicates if the traffic data within the queue of data is permitted to be transmitted.
1. A method, comprising:
(a) receiving traffic data;
(b) storing the traffic data in a data block within a queue of data;
(c) reading a first status information associated with the queue of data, wherein the first status information is stored on a first storage device, and wherein the queue of data is stored on a second storage device; and
(d) transmitting the traffic data if the status information associated with the queue of data indicates that the traffic data is permitted to be transmitted, wherein steps (a) and (b) are performed by a first processor, wherein step (c) is performed by a second processor, wherein step (d) is performed by a third processor, and wherein the first, second, and third processor are collocated on a single processor island.
2. The method of claim 1 , further comprising;
(b1) updating a second status information upon receiving the traffic data, wherein the second status information is a bit indicating if the queue of data contains traffic data, and wherein the second status information is stored in a third storage device.
3. The method of claim 1 , wherein the first status information is a single bit indicating that the traffic data in the queue of data is permitted to be transmitted.
4. The method of claim 1 , wherein the first storage device has a first access rate, wherein the second storage device has a second access rate, and wherein the first access rate is greater than the second access rate.
5. The method of claim 2 further comprising:
(e) updating the first status information based upon a second status information associated with the queue of data, wherein the updating of (e) is performed by a fourth processor that communicates a control message to the second processor, and wherein the second status information is stored in the third storage device.
6. The method of claim 2 , wherein the second storage information is a bit indicating if the queue of data contains traffic data.
7. The method of claim 1 , wherein the reading of (c) is performed by performing a fast bit set lookup.
8. The method of claim 1 , wherein the reading of (c) further comprises:
(c1) scanning a first set of bits, wherein each of the first set of bits indicates if any one of a second set of bits is set, and wherein each of the second set of bits indicates if any one of a third set of bits is set.
9. The method of claim 1 , wherein the first storage device and the third storage device are located on the processor island, and wherein the second storage device is not located on the processor island.
10. The method of claim 1 , wherein the receiving of (a) is performed across a Command/Push/Pull (CPP) bus.
11. The method of claim 1 , wherein the transmitting of (d) is performed in part across a Command/Push/Pull (CPP) bus.
12. The method of claim 1 , wherein the first processor has a dedicated code memory and a dedicated data memory, and wherein the dedicate code memory and dedicated data memory are both located on the processor island.
13. The method of claim 1 , wherein the first and second storage devices are taken from the group consisting of: a register, a plurality of registers, a memory, a plurality of memories.