Digital domain accumulative CMOS-TDI image sensor with low power consumption

1. A digital domain accumulative CMOS-TDI image sensor with low power consumption, comprising a pixel array of n+k lines multiplied m columns, a column parallel signal pre-processing circuit, a column parallel successive approximation (SAR) ADC, a column parallel digital domain accumulator, a column parallel divider, a timing control circuit and an output shift register, wherein n+k+1 coarse quantification memory units are provided to the column parallel digital domain accumulator for storage of coarse quantification results; and memory units for storage of n times of fine quantification results are also provided, thus realizing n stages of TDI signal accumulation after accumulation of n times of fine quantification results; K lines of pre-processing pixels are added into an n×m pixel array (n lines and m columns), the newly added k lines of pre-processing pixels are located to face a direction along which the original pixel array moves towards the object; the coarse quantification memory units, memory units for storage of n times of fine quantification results and the column parallel digital domain accumulator comprise a digital adder, a multiplexer, a memory array A, a memory array B, an one-way bus 1 , a two-way bus 2 , a two-way bus 3 , a two-way bus 4 and an one-way bus 5 ; the memory array A functions to store fine quantification results therein, while the memory array B functions to store coarse quantification results therein; an output end of the SAR ADC is connected to an input end of the digital adder via the one-way bus 1 ; an output end of the digital adder and another input end of the digital adder are connected to the multiplexer through the two-way bus 2 ; a channel B of the multiplexer is connected with the memory array B through the two-way bus 3 ; a channel A of the multiplexer is connected with the memory array A through the two-way bus 4 ; and the memory array B is connected with a DAC of the SAR ADC via the one-way bus 5 .

2. The sensor as recited in claim 1 , wherein the connection and timing control among these coarse quantification memory units, memory units for storage of n times of fine quantification results and the column parallel digital domain accumulator are: the image sensor has original n lines of pixels and newly added k lines of pixels and k lines of pixels added when the image sensor begins to work perform in advance exposure to appeared object A for k times; the output results of P1th line of pixels are coarsely quantified by the column parallel SAR ADC and then are stored into the memory Bn of memory array B of the digital adder; after that, results produced by performing exposure to the same object A by the P2th line of pixels are coarsely quantified by the SAR ADC and the resultant digital signals are transferred to the input end of the digital adder via the bus 1 ; the data stored in the memory Bn is delivered to another input end of the digital adder via the bus 3 and the multiplexer and further via the bus 2 ; finally, the output results of the digital adder are returned back to the memory Bn through the bus 2 , multiplexer and bus 3 ; by the same token, signals outputted by preceding k lines of pixels are accumulated and then stored into the memory Bn; during fine quantification period of the SAR ADC, after the first line of pixels finishes exposure to the object A, the signals outputted by the first line of pixels are delivered to a positive input end of a comparator of the SAR ADC; at the same time, data stored in the memory Bn is averaged by dividing it by k and resultant average value is sent to the DAC of the SAR ADC through the bus 5 ; in this way, on the basis of coarse quantification results, the SAR ADC further performs successive approximation to inputted analog signals so as to perform fine quantification; As such, the output results of the SAR ADC are entire quantification results of the present exposure signals and the quantification results are stored into the memory An; in a similar manner, the signals in the memory An are accumulated n times and then outputted; the output results of the accumulator are transferred to a divider so as to restore digit-bandwidth of the signals and finally, signals of all columns are outputted in serial by the shift register.