III-nitride device and method having a gate isolating structure
A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.
1. A semiconductor device, comprising:
a substrate comprising III-N semiconductor material;
an low-defect layer of III-N semiconductor material disposed on said substrate;
a barrier layer of III-N semiconductor material disposed on said low-defect layer;
a gallium nitride field effect transistor (GaN FET), comprising:
a gate disposed over said barrier layer;
a drain contact disposed over said low-defect layer; and
a source contact disposed over said low-defect layer; and
a gate isolating structure disposed over said barrier layer having a same structure as said gate, said gate isolating structure being operable to electrically isolate a first region of said semiconductor device from a second regions of said semiconductor device.
2. The semiconductor device of claim 1 , in which said gate isolating structure is contiguous with said gate.
3. The semiconductor device of claim 1 , in which said gate isolating structure is separate from said gate.
4. The semiconductor device of claim 1 , in which:
said first region is contiguous with said drain contact; and
said second region is contiguous with said source contact.
5. The semiconductor device of claim 1 , in which:
said GaN FET is a first GaN FET;
said semiconductor device includes a second GaN FET;
said first region is contiguous with said first GaN FET; and
said second region is contiguous with said second GaN FET.
6. The semiconductor device of claim 1 , in which:
said semiconductor device includes an isolation structure; and
said gate isolating structure extends to and overlaps said isolation structure.
7. The semiconductor device of claim 1 , in which said gate isolating structure surrounds an input/output (I/O) structure.
8. The semiconductor device of claim 1 , in which said gate isolating structure surrounds said GaN FET.
9. The semiconductor device of claim 1 , in which said gate isolating structure includes a metal gate layer.
10. The semiconductor device of claim 1 , in which said gate isolating structure includes a semiconductor gate layer of III-N semiconductor material.
11. A method of forming a semiconductor device, comprising the steps of:
providing a substrate comprising III-N semiconductor material;
forming an low-defect layer of III-N semiconductor material on said substrate;
forming a barrier layer of III-N semiconductor material on said low-defect layer;
forming a GaN FET, by a process comprising the steps of:
forming a gate over said barrier layer;
forming a drain contact over said low-defect layer; and
forming a source contact over said low-defect layer; and
forming a gate isolating structure over said barrier layer concurrently with said gate, said gate isolating structure being operable to electrically isolate a first region of said semiconductor device from a second regions of said semiconductor device.
12. The method of claim 11 , in which said gate isolating structure is contiguous with said gate.
13. The method of claim 11 , in which said gate isolating structure is separate from said gate.
14. The method of claim 11 , in which:
said first region is contiguous with said drain contact; and
said second region is contiguous with said source contact.
15. The method of claim 11 , in which said GaN FET is a first GaN FET, and further including the step of forming a second GaN FET, in which:
said first region is contiguous with said first GaN FET; and
said second region is contiguous with said second GaN FET.
16. The method of claim 11 , further including the step of forming an isolation structure, and said gate isolating structure is formed to extend to and overlap said isolation structure.
17. The method of claim 11 , in which said gate isolating structure surrounds an input/output (I/O) structure.
18. The method of claim 11 , in which said gate isolating structure surrounds said GaN FET.
19. The method of claim 11 , in which said step of forming said gate isolating structure includes forming a metal gate layer.
20. The method of claim 11 , in which said step of forming said gate isolating structure includes forming a semiconductor gate layer of III-N semiconductor material.