Method and system for single root input/output virtualization virtual functions sharing on multi-hosts

1. A method for single-root input/output virtualization (SR-IOV) virtual functions sharing on one or more hosts, implemented in a management system connected to the one or more hosts by a transparent bridge device, comprising:

simulating one or more simulated devices in the one or more hosts with each simulated device mapped to one of a plurality of SR-IOV virtual functions of a SR-IOV device;

redirecting each of one or more configuration spaces from a corresponding one of the plurality of SR-IOV virtual functions to a corresponding one of the one or more simulated devices in the one or more hosts, through a non-transparent bridge (NTB) device in each of the one or more hosts, wherein the one or more hosts is connected with the transparent bridge device by the respective NTB device in each of the one or more hosts;

redirecting each of one or more configuration space requests from the corresponding one of the one or more simulated devices to a corresponding SR-IOV virtual function of the corresponding one of the one or more simulated devices when the configuration space request is received by the corresponding one of the one or more simulated devices; and

redirecting each of one or more memory access operations from the corresponding SR-IOV virtual function to a mapped memory on a corresponding host of the one or more hosts having the corresponding one of the one or more simulated devices; and

redirecting each of one or more interrupts generated by one or more SR-IOV virtual machines hosted on the one or more hosts to the corresponding one of the one or more simulated devices,

wherein each of the one or more hosts has an address space of the respective host and the management system has a corresponding direct memory access (DMA) descriptor for the one or more virtual functions of the corresponding host, and wherein a full range of a corresponding random access memory of the corresponding host in the address space of the respective host is all mapped into an unoccupied address space of the management system through the NTB device in each of the one or more hosts.

2. The method as claimed in claim 1 , wherein the one or more simulated devices are simulated by each of one or more kernels in the one or more hosts.

3. The method as claimed in claim 2 , wherein the one or more simulated devices are simulated by interpreting one or more read or write routines in a kernel of one of the one or more hosts and feeding back a correct response when the kernel accesses the one or more simulated devices.

4. The method as claimed in claim 1 , wherein the mapped memory acts as a direct memory access buffer, and a Message-Signaled-Interrupt (MSI) address of the corresponding SR-IOV virtual function is remapped to a MSI address of the corresponding host having the corresponding one of the one or more simulated devices.

5. The method as claimed in claim 1 , wherein each of the one or more SR-IOV virtual machines on the one or more hosts is allowed to share the plurality of SR-IOV virtual functions of the SR-IOV device.

6. The method as claimed in claim 1 , wherein through each of the NTB device in the one or more hosts, an original SR-IOV virtual function driver is to work directly on the one or more hosts and the one or more SR-IOV virtual machines with a data zero-copy operation.

7. The method as claimed in claim 1 , wherein said method further includes:

enabling a first input/output memory management unit (IOMMU) in the management system and a second IOMMU in each of the one or more hosts;

configuring the first IOMMU and the second IOMMU and a NTB remapping of a memory address and an interrupt address; and

redirecting a DMA address from the plurality of SR-IOV virtual functions to a corresponding memory in each of the one or more hosts when an original virtual function driver allocates a DMA memory.

8. The method as claimed in claim 7 , wherein the first IOMMU in the management system limits a memory access range of the plurality of virtual functions and the one or more simulated devices.

9. The method as claimed in claim 7 , wherein the second IOMMU in each of the one or more hosts limits each of the one or more simulated devices from accessing memories of other simulated devices.

10. The method as claimed in claim 7 , wherein the DMA address in the DMA descriptor is redirected from the plurality of SR-IOV virtual functions to a data buffer in each of the one or more hosts, and the plurality of SR-IOV virtual functions on the management system access the data buffer in the respective host by a DMA operation.