Double-sampling receiver with dynamic offset modulation for optical and electrical signaling
A receiver architecture is disclosed which employs an RC double-sampling front-end and dynamic offset modulation technique. A low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in typical transimpedance-amplifier (TIA) receivers. In addition, a demultiplexed output of the receiver helps save power in the subsequent digital blocks. Various applications are described including optical receivers, electrical on-chip interconnects, as well as pulse amplitude modulation. The receiver can be implemented in CMOS and is scalable and portable to other technologies.
1. An apparatus for signal receiving, comprising:
a front-end for signal communication including:
a double sampling circuit for sampling an input voltage, at the end of two consecutive bit times, producing a voltage difference used to determine a signal received on the front end; and
a dynamic offset modulation (DOM) circuit for applying a dynamic offset voltage to the voltage difference, wherein the DOM circuit avoids input-dependent performance degradation and the front-end has a bandwidth that is at least an order of magnitude less than a bandwidth of the signal.
2. The apparatus of claim 1 , wherein a binary output representing the signal is determined from the voltage difference with the applied dynamic offset voltage.
3. The apparatus of claim 1 , wherein a gain of the dynamic offset voltage is (1−e −T/τ ) where T is a bit time and τ is an RC time constant of the front-end.
4. The apparatus of claim 1 , wherein the input voltage is from an on-chip interconnect.
5. The apparatus of claim 1 , wherein the input voltage is from a photodiode receiving light.
6. The apparatus of claim 1 , wherein the input voltage is a pulse amplitude modulation signal.
7. The apparatus of claim 1 , wherein the front-end, the double sampling circuit, and the offset voltage circuit are implemented in complementary metal oxide semiconductor (CMOS).
8. The apparatus of claim 1 , wherein the front-end comprises an RC circuit and a resistance R in the RC circuit is a low-bandwidth Trans Impedance Amplifier (TIA).
9. The apparatus of claim 8 , wherein the TIA's bandwidth is less than 10% of the operating data rate 1/T b .
10. The apparatus of claim 1 , wherein the front-end is for low power (less than 0.5 pJ/s) and high speed (higher than 20 Gb/s) signal communication.
11. The apparatus of claim 1 , wherein the apparatus is scalable and portable.
12. The apparatus of claim 1 , wherein the double sampling circuit performs de-multiplexing.
13. The apparatus of claim 1 , wherein:
the signal is data bit sequence, wherein each bit in the sequence is indexed by an integer n and the front-end's input produces a front-end signal in response thereto;
the front-end includes a resistor-capacitor (RC) circuit that integrates the front-end signal to produce an exponential signal, wherein a time constant RC=τ of the RC circuit is greater than a bit time T of the data bit sequence;
the double sampling circuit samples a first level V(n−1) of the exponential signal and a next level V(n) at the bit time T later of the exponential signal,
the voltage difference V[n]=V(n)−V(n−1), V[n]>0 indicates the n th bit is a one, and V[n]<0 indicates the n th bit is a zero;
the DOM circuit converts V[n] into a V′[n] having a constant magnitude if the V[n] is different from the constant magnitude;
a sense amplifier or comparator receives the V′[n] or the V[n] having the constant magnitude at its input to read each data bit in the data bit sequence; and
an isolation or buffer amplifier isolates the sense amplifier from the double sampling circuit.
14. The apparatus of claim 13 , wherein the constant magnitude is α/2(1−e −T/τ ) and α is a gain between the double sampling circuit and the input of the sense amplifier.
15. The apparatus of claim 13 , wherein:
the RC circuit comprises a parasitic capacitance C and a resistance of the front-end's input, and a shunt resistor R in parallel with the resistance, and
RC=τ is given by the product of the resistance of R and the parasitic capacitance C, such that an output of the front-end's input in response to the data bit sequence is integrated over the parasitic capacitance to produce the exponential signal.
16. The apparatus of claim 15 , wherein:
the signal is a current detected by a photodiode having the parasitic capacitance, and
the exponential voltage signal across the parasitic capacitance and applied to the double sampling circuit is V PD =V DD −RI 1 e −t/RC , where t is time, I 1 is the current generated by the front-end's input in response to a bit comprising a one, V DD is a voltage of a power rail of the front-end, and R is selected to prevent out of range input voltages that would saturate the sense amplifier or comparator.
17. A method for signal receiving, comprising:
receiving an input voltage at a front-end including a transimpedance amplifier (TIA) coupled to a capacitor;
sampling the input voltage at an end of two consecutive bit times and determining a voltage difference of the sampled input voltage at the end of the two consecutive bit times, using a double sampling circuit; and
applying a dynamic offset voltage to the voltage difference with an offset voltage circuit.
18. The method of claim 17 , wherein a binary output representing the signal is determined from the voltage difference with the applied dynamic offset voltage.
19. The apparatus of claim 17 , wherein a gain of the dynamic offset voltage is (1−e −T/τ ) where T is a bit time and τ is an RC time constant of the front end.
20. The method of claim 17 , wherein the input voltage is from an on-chip interconnect.
21. The method of claim 17 , wherein the input voltage is from a photodiode receiving light.
22. The method of claim 17 , wherein the input voltage is a pulse amplitude modulation signal.
23. The method of claim 17 , wherein a front-end, the double sampling circuit, and the offset voltage circuit are implemented in complementary metal oxide semiconductor (CMOS).
24. The method of claim 17 , wherein the TIA's bandwidth is less than 10% of the operating data rate 1/T b .