Discrete semiconductor device package and manufacturing method
View Patent ↗Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.
1. A discrete semiconductor device package comprising:
a vertical semiconductor device, integral to the discrete semiconductor device package, including,
a semiconductor die, with a lateral dimension, having a first surface and a second surface opposite said first surface, said second surface carrying an electrical contact;
the semiconductor die having a P-doped region, an N-doped region and a PN junction area therebetween, wherein the semiconductor die is oriented vertically for passing current vertically relative to the lateral dimension:
a conductive body electrically connected on said electrical contact of the semiconductor die of the vertical semiconductor device, wherein the conductive body has a lateral dimension smaller than the lateral dimension of the semiconductor die;
an encapsulation material formed on top of the second surface to laterally encapsulate said conductive body; and
a capping member in electrical contact with the conductive body, said capping member extending over the encapsulation material.
2. The discrete semiconductor device package of claim 1 , wherein the capping member comprises a further semiconductor die or a solder cap.
3. The discrete semiconductor device package of claim 2 , further comprising a solder cap on the further semiconductor die.
4. The discrete semiconductor device package of any of the preceding claims, further comprising a further solder cap in conductive contact with the first surface.
5. The discrete semiconductor device package of any of the preceding claims, wherein the conductive body has a ball or pillar shape.
6. The discrete semiconductor device package of any of the preceding claims, wherein the encapsulation material also extends along the respective sides of the semiconductor die that connect the first surface to the second surface.
7. A carrier comprising a first carrier contact and a second carrier contact, said carrier further comprising the discrete semiconductor device package of claim 1 , wherein the first carrier contact is conductively connected to the first surface and the second carrier contact is conductively connected to the conductive body by respective solder portions.
8. The discrete semiconductor device package of claim 1 , wherein the semiconductor die having a P-doped region, an N-doped region and a PN junction area is a diode.
9. The discrete semiconductor device package of claim 8 , wherein the P-doped region of the diode is located below or above the N-doped region.