Fully molded fan-out

1. A method of making a semiconductor device, comprising:

providing a semiconductor die comprising a spacer element coupled to a first surface of the semiconductor die;

coupling the spacer element to a carrier to create a gap between the first surface of the semiconductor die and the carrier;

disposing a mold compound around the semiconductor die and within the gap; and

uncoupling the spacer element from the carrier after the mold compound is disposed around the semiconductor die.

2. The method of claim 1 , further comprising:

thinning a semiconductor wafer on which the semiconductor die is constructed prior to disposing the mold compound; and

dicing the semiconductor wafer to separate the semiconductor die from a plurality of other semiconductor die.

3. The method of claim 1 , further comprising disposing the mold compound as part of a compression molding process.

4. The method of claim 1 , further comprising:

disposing a first portion of the mold compound over the first surface of the semiconductor die; and

disposing a second portion of the mold compound over a second surface of the semiconductor die opposite the first surface of the semiconductor die, wherein a thickness of the second portion of the mold compound is less than three times a thickness of the first portion of the mold compound.

5. The method of claim 4 , further comprising:

providing bond pads on the first surface of the semiconductor die; and

forming the spacer element as a plurality of conductive posts coupled to the bond pads.

6. The method of claim 5 , further comprising constructing a fan-in redistribution layer (RDL) structure on the first surface of the semiconductor die that electrically couples the bond pads to the plurality of conductive posts.

7. The method of claim 1 , further comprising constructing a fan-out redistribution layer (RDL) on a surface of the mold compound and electrically coupled with the spacer element.

8. A method of making a semiconductor device, comprising:

constructing a spacer element coupled with a surface of a semiconductor die, wherein the spacer element is configured to create a gap between the semiconductor die and a surface of a temporary carrier; and

encapsulating the semiconductor die within a mold compound, wherein the encapsulating comprises introducing the mold compound into the gap.

9. The method of claim 8 , further comprising attaching the spacer element to the temporary carrier prior to introducing the mold compound into the gap.

10. The method of claim 8 , wherein encapsulating the semiconductor die within the mold compound further comprises performing a compression molding process.

11. The method of claim 8 , further comprising reducing warpage of the semiconductor device by encapsulating the semiconductor die with a first thickness of the mold compound disposed over a first surface of the semiconductor die and a second thickness of the mold compound similar to the first thickness disposed over a second surface of the semiconductor die opposite the first surface.

12. The method of claim 8 , further comprising:

providing at least one bond pad on the surface of the semiconductor die; and

constructing the spacer element to comprise at least one conductive element that is electrically coupled with the at least one bond pad of the semiconductor die.

13. The method of claim 12 , further comprising:

constructing a fan-in redistribution layer (RDL) structure coupled with the at least one bond pad of the semiconductor die prior to encapsulating the semiconductor die within the mold compound; and

plating the at least one conductive element onto the fan-in RDL structure.

14. The method of claim 13 , further comprising constructing a fan-out redistribution layer (RDL) structure on a surface of the mold compound that is electrically coupled with the at least one conductive element.

15. The method of claim 14 , further comprising applying a plurality of solder balls to the fan-out RDL structure to create a ball-grid array (BGA) package.

16. A method of making a semiconductor device, comprising:

coupling a semiconductor die to a carrier with mounting tape;

substantially encapsulating the semiconductor die within a mold compound while the semiconductor die is face down on the carrier; and

constructing a redistribution layer (RDL) structure electrically connecting bond pads of the semiconductor die to conductive material at an exterior surface of the semiconductor device.

17. The method of claim 16 , wherein encapsulating the semiconductor die within the mold compound further comprises:

creating a gap between the semiconductor die and a surface of the carrier supporting the semiconductor die; and

filling the gap with the mold compound.

18. The method of claim 16 , further comprising:

constructing a plurality of conductive posts electrically coupled with the bond pads of the semiconductor die; and

attaching the conductive posts to a surface of a carrier, wherein the plurality of conductive posts are configured to maintain a gap between the semiconductor die and a surface of a carrier.

19. The method of claim 16 , further comprising:

constructing a fan-in redistribution layer (RDL) structure on a surface of the semiconductor die that is configured to electrically couple the bond pads to a plurality of conductive posts; and

forming the RDL as a fan-out RDL electrically coupled to the plurality of conductive posts after substantially encapsulating the semiconductor die within the mold compound.

20. The method of claim 16 , wherein substantially encapsulating the semiconductor die within the mold compound further comprises disposing the mold compound over six sides of the semiconductor die.