IP Library › Granted Patent US 9,741,851
Granted Patent B2
US 9,741,851 · App. 13/892,312 · Granted Aug 22, 2017

Trench junction barrier controlled Schottky

Inventors: Sik K Lui (Sunnyvale, CA); Anup Bhalla (Santa Clara, CA)
Assignee: Alpha and Omega Semiconductor Incorporated
H01L29/7839H01L29/0619H01L29/0623H01L29/66143H01L29/66712H01L29/7806H01L29/7813H01L29/872
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Quick Facts
Patent No.
US 9,741,851
App. No.
13/892,312
Granted
Aug 22, 2017
Kind
B2
Abstract

A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

Claims (37)

1. A metal oxide semiconductor field effect transistor (MOSFET) device comprising a plurality of transistor cells wherein each cell having a gate surrounded by body regions encompassing a source region for controlling and conducting a current between the source region near a top surface of a semiconductor substrate and a drain region disposed on a bottom surface of the semiconductor substrate wherein the MOSFET wherein:

the semiconductor substrate having a first conductivity type with a top dopant layer of a second conductivity type below a top surface of the semiconductor substrate;

a trench disposed between the gates of two adjacent transistor cells and a trench bottom dopant region having a same conductivity type as the body region surrounded a bottom surface of the trench wherein the trench having sidewalls covering with a Schottky lining extending from a bottom of the top dopant layer to a top of the bottom dopant region and wherein the trench is filled with a conductive material extending below the body region of the MOSFET; and

dopant regions having the same conductivity type as the body region surrounded a top-portion of the trench and intermediate dopant regions having the same conductivity type as the body region surrounded a mid-portion of the trench.

2. The MOSFET device of claim 1 wherein:

the trench is filled with a Schottky barrier metal.

3. The MOSFET device of claim 1 wherein:

the trench is filled with a Ti/TiN metal as a Schottky barrier metal.

4. The MOSFET of claim 1 wherein:

the trench bottom dopant region completely surrounding the bottom surface of the trench.

5. The MOSFET device of claim 1 wherein:

the conductive material filling in the trench comprising a barrier metal overlaying a top surface of the semiconductor substrate forming a Schottky junction with said semiconductor substrate in an area between the gates of the adjacent transistor cells.

6. The MOSFET device of claim 1 wherein:

said trench comprising non-rounded trench corners near the bottom surface of the trench.

7. The MOSFET device of claim 1 wherein:

the gate is a planar gate comprising a conductive layer extended laterally over substantially a mid-porting in each of the transistor cell above the body and source regions.

8. The MOSFET device of claim 1 wherein:

the gate is a trench gate comprising a gate-trench filled with a gate conductive material extended vertically in substantially a mid-porting of each of the transistor cell surrounded by the body and source regions.

9. The MOSFET device of claim 1 wherein:

the trench is filled with a Schottky barrier metal constituting an integrated trench junction barrier Schottky (TJBS) diode.

10. A method for manufacturing an integrated trench junction barrier Schottky (TJBS) diode for a MOSFET device wherein the MOSFET device comprising a plurality of transistor cells and each cell having a gate surrounded by body regions encompassing a source region for controlling and conducting a current between the source region near a top surface of a semiconductor substrate and a drain region disposed on a bottom surface of the semiconductor substrate, the method comprising:

providing a semiconductor substrate of a first conductivity type and forming a top dopant layer of a second conductivity type below a top surface of the semiconductor substrate;

opening a trench between the gates of two adjacent transistor cells through the top dopant layer to a predetermined depth and implanting a dopant of the second conductivity type through the trench to form a bottom dopant region below the trench;

lining a Schottky barrier metal layer on sidewalls of the trench extending from a bottom of said top dopant layer to a top of said bottom dopant region; and

forming an intermediate dopant region of said second conductivity type surrounding the sidewalls of the trench at a top-portion of the trench and at a mid-portion of the trench.

11. The method of claim 10 further comprising:

implanting at substantially at a zero degree into said trench for doping the bottom dopant region of said second conductivity type surrounding a bottom surface of said trench.

12. The method of claim 10 further comprising:

filling said trench with a Schottky barrier metal.

13. The method of claim 10 wherein:

said step of opening a trench in a semiconductor substrate of the first conductivity type is a step of opening said trench in a N-type semiconductor substrate and doping said dopant region with a P-dopant.

14. The method of claim 10 further comprising:

filling said trench with a Ti/TiN metal as a Schottky barrier metal.

15. The method of claim 10 wherein:

filling said trench with a tungsten metal as a Schottky barrier metal.

16. The method of the claim 10 wherein:

said step of opening said trench to said predetermined depth comprising step of opening said trench to said predetermined depth with non-rounded trench corners.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2013
From: LUI, SIK K; BHALLA, ANUP
To: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
Reel/Frame 030420/0668 →
Continuity (1)
Related Publication 20140332882A1 · Nov 13, 2014