Stacked semiconductor nanowires with tunnel spacers
View Patent ↗A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material. A gate structure is formed within the areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material.
1. A method of forming a semiconductor structure, said method comprising:
providing at least one multilayered stacked semiconductor material structure on a semiconductor substrate and at least one sacrificial gate material structure straddling a portion of the at least one multilayered stacked semiconductor structure, wherein the at least one multilayered stacked semiconductor material structure includes alternating layers of a sacrificial semiconductor material and a semiconductor nanowire template material, said sacrificial semiconductor material is a different semiconductor material than said semiconductor nanowire template material;
replacing end segments of each layer of sacrificial semiconductor material with a dielectric spacer structure;
forming a source region and a drain region from exposed sidewall surfaces of each layer of semiconductor nanowire template material and on opposite sides of the at least one sacrificial gate material;
suspending each layer of semiconductor nanowire template material of the least one multilayered stacked semiconductor material structure by removing the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material; and
forming a gate structure within areas previously occupied by the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material.
2. The method of claim 1 , wherein said providing the least one multilayered stacked semiconductor material structure comprises:
forming a base sacrificial semiconductor layer on an upper surface of the semiconductor substrate;
forming a semiconductor material stack comprising alternating layers of said sacrificial semiconductor material, and said semiconductor nanowire template material, with the proviso that at least two layers of each material is present, and that the topmost layer of the semiconductor material stack comprises said semiconductor nanowire template material; and
patterning the semiconductor material stack and the base sacrificial semiconductor layer by lithography and etching.
3. The method of claim 2 , wherein during said etching, trenches are formed within the semiconductor substrate, and wherein said trenches are filled with a trench dielectric material providing trench isolation structures.
4. The method of claim 1 , wherein said providing the at least one sacrificial gate material structure comprises:
depositing a blanket layer of sacrificial gate material; and
patterning the blanket layer of sacrificial gate material by lithography and etching.
5. The method of claim 1 , wherein other dielectric spacers are formed on exposed sidewall surfaces of the at least one sacrificial gate material structure prior to replacing end segments of each layer of sacrificial semiconductor material with the dielectric spacer.
6. The method of claim 1 , wherein said replacing end segments of each layer of sacrificial semiconductor material with the dielectric spacer comprises:
removing said end segments of each layer of sacrificial semiconductor material by etching; and
depositing a spacer material.
7. The method of claim 1 , wherein said forming the source region and the drain region from exposed sidewall surfaces of each layer of semiconductor nanowire template material and on opposite sides of the at least one sacrificial gate material structure comprises forming a doped semiconductor material utilizing an in-situ epitaxial deposition process.
8. The method of claim 1 , wherein said forming the source region and the drain region from exposed sidewall surfaces of each layer of semiconductor nanowire template material and on opposite sides of the at least one sacrificial gate material structure comprises forming a non-doped semiconductor material by epitaxial growth, and subjecting the non-doped semiconductor material to ion implantation or gas phase doping.
9. The method of claim 1 , wherein said gate structure formed in the area previously occupied by the at least one sacrificial gate material structure comprises a U-shaped gate dielectric having a bottommost portion in direct contact with an upper surface of a topmost layer of a suspended semiconductor material and a gate conductor located on the U-shaped gate dielectric.
10. The method of claim 1 , wherein each gate structure formed in the area previously occupied by remaining portions of the sacrificial semiconductor material comprises a gate dielectric that surrounds a gate conductor.