Patent Assignment
Reel/Frame 051489/0557
Assignment of Assignor's Interest
Recorded: 2020-01-06
Pages: 23
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2019-12-27
Assignee
TESSERA, INC.
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(327)
Method and Apparatus for Forming Nickel Silicide with Low Defect Density in Fet Devices
Increasing Electromigration Lifetime and Current Density in Ic Using Vertically Upwardly Extending Dummy Via
Low Resistance and Inductance Backside Through Vias and Methods of Fabricating Same
Increasing Electromigration Lifetime and Current Density in Ic Using Vertically Upwardly Extending Dummy Via
Microstructure Modification in Copper Interconnect Structure
Method and Apparatus for Forming Nickel Silicide with Low Defect Density in Fet Devices
Method and Apparatus for Forming Nickel Silicide with Low Defect Density in Fet Devices
Low Resistance and Inductance Backside Through Vias and Methods of Fabricating Same
Integrated Decoupling Capacitor Employing Conductive Through-Substrate Vias
Chip Guard Ring Including a Through-Substrate Via
Integrated Structures of High Performance Active Devices and Passive Devices
Microstructure Modification in Copper Interconnect Structure
Hybrid Bonding Techniques for Multi-Layer Semiconductor Stacks
Interconnect Structures Incorporating Air-Gap Spacers
Interconnect Structures Incorporating Air-Gap Spacers
Spin Transfer Torque Cell for Magnetic Random Access Memory
Wafer-Scale Package Structures with Integrated Antennas
Hybrid Bonding Techniques for Multi-Layer Semiconductor Stacks
Integrated Structures of High Performance Active Devices and Passive Devices
Multi-Layer Work Function Metal Replacement Gate
Multi-Layer Work Function Metal Replacement Gate
Patent:
8,647,972 →
Application:
13/618,255 →
Graphene and Metal Interconnects
Overlap Capacitance Nanowire
Self-Forming Embedded Diffusion Barriers
Stacked Semiconductor Nanowires with Tunnel Spacers
Overlap Capacitance Nanowire
Integrated Decoupling Capacitor Employing Conductive Through-Substrate Vias
Stacked Semiconductor Nanowires with Tunnel Spacers
Copper Wire and Dielectric with Air Gaps
Fin Density Control of Multigate Devices Through Sidewall Image Transfer Processes
Fin End Spacer for Preventing Merger of Raised Active Regions
Gate Structure Integration Scheme for Fin Field Effect Transistors
Very Planar Gate Cut Post Replacement Gate Process
Lowering Parasitic Capacitance of Replacement Metal Gate Processes
Methods and Structure to Form High K Metal Gate Stack with Single Work-Function Metal
Dielectric Liner for a Self-Aligned Contact via Structure
Semiconductor Device Including Merged-Unmerged Work Function Metal and Variable Fin Pitch
Self-Aligned Contact Process Enabled by Low Temperature
Sti Region for Small Fin Pitch in Finfet Devices
Method and Structure for Robust Finfet Replacement Metal Gate Integration
Silicon Nanowire Formation in Replacement Metal Gate Process
Selective Removal of Semiconductor Fins
Finfet with Constrained Source-Drain Epitaxial Region
Heterogeneous Source Drain Region and Extension Region
Semiconductor Device with Reduced via Resistance
Interconnect Structure with Capping Layer and Barrier Layer
Self-Aligned Quadruple Patterning Process
Fin Cut on Sit Level
Patent:
9,269,627 →
Application:
14/501,654 →
Dielectric Liner for a Self-Aligned Contact via Structure
Copper Wire and Dielectric with Air Gaps
Air Gap Semiconductor Structure with Selective Cap Bilayer
Patent:
9,305,836 →
Application:
14/536,751 →
Replacement Metal Gate Dielectric Cap
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Spin Transfer Torque Cell for Magnetic Random Access Memory
Graphene and Metal Interconnects with Reduced Contact Resistance
Optimized Wires for Resistance or Electromigration
Method of Forming Performance Optimized Gate Structures by Silicidizing Lowered Source and Drain Regions
Punch Through Stopper in Bulk Finfet Device
Finfet Device with Vertical Silicide on Recessed Source/Drain Epitaxy Regions
Method of Forming Contact Useful in Replacement Metal Gate Processing and Related Semiconductor Structure
Patent:
9,337,094 →
Application:
14/589,222 →
Silicon Nitride Fill for Pc Gap Regions to Increase Cell Density
Trenched Gate with Sidewall Airgap Spacer
Air Gap Contact Formation for Reducing Parasitic Capacitance
Iii-V Compound and Germanium Compound Nanowire Suspension with Germanium-Containing Release Layer
Patent:
9,390,980 →
Application:
14/666,520 →
Overlap Capacitance Nanowire
Stable Multiple Threshold Voltage Devices on Replacement Metal Gate Cmos Devices
Minimizing Shorting Between Finfet Epitaxial Regions
Patent:
9,443,853 →
Application:
14/680,099 →
Fin Density Control of Multigate Devices Through Sidewall Image Transfer Processes
Spin Transfer Torque Cell for Magnetic Random Access Memory
Dual Work Function Integration for Stacked Finfet
Patent:
9,356,027 →
Application:
14/708,885 →
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Sidewall Image Transfer Process for Fin Patterning
Patent:
9,287,135 →
Application:
14/721,430 →
Method to Form Stacked Germanium Nanowires and Stacked Iii-V Nanowires
Patent:
9,437,502 →
Application:
14/738,316 →
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Stable Multiple Threshold Voltage Devices on Replacement Metal Gate Cmos Devices
Perpendicular Magnetic Anisotropy Free Layers with Iron Insertion and Oxide Interfaces for Spin Transfer Torque Magnetic Random Access Memory
Insulating a via in a Semiconductor Substrate
Low Resistance Metal Contacts to Interconnects
Finfet Devices
Structure and Fabrication Method for Electromigration Immortal Nanoscale Interconnects
Patent:
9,418,934 →
Application:
14/754,999 →
Silicon Nanowire Formation in Replacement Metal Gate Process
Self-Forming Embedded Diffusion Barriers
Semiconductor Device Including Merged-Unmerged Work Function Metal and Variable Fin Pitch
Method for Manufacturing Interconnect Structures Incorporating Air Gap Spacers
Interconnect Structures Incorporating Air-Gap Spacers
Finfet Device Formed by a Replacement Metal-Gate Method Including a Gate Cut-Last Step
Asymmetric Finfet Memory Access Transistor
Patent:
9,583,624 →
Application:
14/865,276 →
Bulk Fin Sti Formation
Methods for Removal of Selected Nanowires in Stacked Gate All Around Architecture
Interconnect Structure with Barrier Layer
Copper Wire and Dielectric with Air Gaps
Fin End Spacer for Preventing Merger of Raised Active Regions
Fin End Spacer for Preventing Merger of Raised Active Regions
Fin End Spacer for Preventing Merger of Raised Active Regions
Low Resistance Contact Structures Including a Copper Fill for Trench Structures
Low Resistance Contact Structures for Trench Structures
Bulk Nanosheet with Dielectric Isolation
Finfet with Constrained Source-Drain Epitaxial Region
Fin Cut Without Residual Fin Defects
Nanosheet Mosfet with Full-Height Air-Gap Spacer
Patent:
9,362,355 →
Application:
14/940,685 →
Self Aligned Replacement Metal Source/Drain Finfet
Patent:
9,466,693 →
Application:
14/943,652 →
Hybrid Airgap Structure with Oxide Liner
Patent:
9,449,871 →
Application:
14/944,355 →
Stable Work Function for Narrow-Pitch Devices
Patent:
9,583,486 →
Application:
14/946,245 →
Fin Pitch Scaling for High Voltage Devices and Low Voltage Devices on the Same Wafer
Low Resistance Metal Contacts to Interconnects
Middle-Of-Line (Mol) Capacitance Reduction for Self-Aligned Contact in Gate Stack
Semiconductor Device Replacement Metal Gate with Gate Cut Last in Rmg
Advanced Copper Interconnects with Hybrid Microstructure
Channel Strain and Controlling Lateral Epitaxial Growth of the Source and Drain in Finfet Devices
Patent:
9,431,486 →
Application:
14/953,851 →
Gate Structure Integration Scheme for Fin Field Effect Transistors
Stress Retention in Fins of Fin Field-Effect Transistors
Mandrel Removal Last in Lateral Semiconductor Growth and Structure for Same
Patent:
9,455,347 →
Application:
14/959,046 →
Air Gap Semiconductor Structure with Selective Cap Bilayer
Method of Forming an Air Gap Semiconductor Structure with Selective Cap Bilayer
Asymmetric Finfet Memory Access Transistor
Patent:
9,553,173 →
Application:
14/962,082 →
BULK SILICON GERMANIUM FinFET
Sram Design to Facilitate Single Fin Cut in Double Sidewall Image Transfer Process
Patent:
9,564,446 →
Application:
14/971,212 →
Advanced Manganese/Manganese Nitride Cap/Etch Mask for Air Gap Formaton Scheme in Nanocopper Low-K Interconnect
Patent:
9,349,687 →
Application:
14/975,725 →
Sidewall Image Transfer Nanosheet
Lowering Parasitic Capacitance of Replacement Metal Gate Processes
Fin Field-Effect Transistor (Finfet) with Reduced Parasitic Capacitance
Gate Structure Integration Scheme for Fin Field Effect Transistors
Gate Stack with Tunable Work Function
Patent:
9,583,400 →
Application:
14/996,563 →
Interconnect Scaling Method Including Forming Dielectric Layer Over Subtractively Etched First Conductive Layer and Forming Second Conductive Material on Dielectric Layer
Patent:
9,502,350 →
Application:
15/009,108 →
Stacked Nanowire Devices
Patent:
9,484,267 →
Application:
15/015,347 →
Nanowire with Sacrificial Top Wire
Fin Cut on Sit Level
Self-Aligned Quadruple Patterning Process
Channel Strain and Controlling Lateral Epitaxial Growth of the Source and Drain in Finfet Devices
Patent:
9,461,168 →
Application:
15/046,559 →
Interconnect Structures Incorporating Air Gap Spacers
Fin Type Field Effect Transistors with Different Pitches and Substantially Uniform Fin Reveal
Patent:
9,691,765 →
Application:
15/063,735 →
Performance Optimized Gate Structures Having Memory Device and Logic Device, the Memory Device with Silicided Source/Drain Regions That Are Raised with Respect to Silicided Source/Drain Regions of the Logic Device
Semiconductor Device with Reduced via Resistance
Self-Aligned Contact Process Enabled by Low Temperature
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Semiconductor Device with Reduced via Resistance
Spin Transfer Torque Cell for Magnetic Random Access Memory
Semiconductor Interconnect Structure with Double Conductors
Forming Gates with Varying Length Using Sidewall Image Transfer
Iii-V Semiconductor Devices with Selective Oxidation
Self Aligned Replacement Metal Source/Drain Finfet
Semiconductor Device with Different Fin Pitches
Nanosheet Mosfet with Full-Height Air-Gap Spacer
Patent:
9,508,829 →
Application:
15/146,031 →
Dual Work Function Integration for Stacked Finfet
Dual Work Function Integration for Stacked Finfet
Hybrid Subtractive Etch/Metal Fill Process for Fabricating Interconnects
Hybrid Subtractive Etch/Metal Fill Process for Fabricating Interconnects
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Hybrid Airgap Structure with Oxide Liner
Interconnect Structure Having Subtractive Etch Feature and Damascene Feature
Patent:
9,601,426 →
Application:
15/166,570 →
Semiconductor Device with Different Fin Pitches
Patent:
9,589,956 →
Application:
15/172,593 →
Semiconductor Device with Different Fin Pitches
Patent:
9,653,463 →
Application:
15/172,598 →
Air Gap Spacer for Metal Gates
Patent:
9,608,065 →
Application:
15/173,132 →
Forming Insulator Fin Structure in Isolation Region to Support Gate Structures
Fin End Spacer for Preventing Merger of Raised Active Regions
Iii-V Compound and Germanium Compound Nanowire Suspension with Germanium-Containing Release Layer
Finfet Devices
Finfet Devices
Replacement Metal Gate Dielectric Cap
Finfet Device with Vertical Silicide on Recessed Source/Drain Epitaxy Regions
Copper Interconnect Structures
Patent:
9,806,018 →
Application:
15/186,600 →
Replacement Metal Gate Dielectric Cap
Structure and Method for Improved Stabilization of Cobalt Cap and/or Cobalt Liner in Interconnects
Patent:
9,780,035 →
Application:
15/198,721 →
Method for Wafer-Wafer Bonding
3D Bonded Semiconductor Structure with an Embedded Capacitor
Patent:
9,716,088 →
Application:
15/199,052 →
3D Bonded Semiconductor Structure with an Embedded Resistor
Patent:
9,620,479 →
Application:
15/199,129 →
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Patent:
9,768,072 →
Application:
15/199,352 →
Minimizing Shorting Between Finfet Epitaxial Regions
Semiconductor Structures Including Middle-of-Line (Mol) Capacitance Reduction for Self-Aligned Contact in Gate Stack
Stacked Nanowire Devices
Finfet with Constrained Source-Drain Epitaxial Region
Method of Forming Performance Optimized Gate Structures by Silicidizing Lowered Source and Drain Regions
Interconnect Structure
Improving Channel Strain and Controlling Lateral Epitaxial Growth of the Source and Drain in Finfet Devices
Low Resistance Contact Structures for Trench Structures
Low Resistance Contact Structures for Trench Structures
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Minimizing Shorting Between Finfet Epitaxial Regions
Multi-Level Metallization Interconnect Structure
Multi-Layer Filled Gate Cut to Prevent Power Rail Shorting to Gate Structure
Patent:
9,805,983 →
Application:
15/241,898 →
Heterogeneous Source Drain Region and Extension Region
Punch Through Stopper in Bulk Finfet Device
Punch Through Stopper in Bulk Finfet Device
Low Aspect Ratio Interconnect
Uniform Fin Dimensions Using Fin Cut Hardmask
Gate Cut with Integrated Etch Stop Layer
Forming a Hybrid Channel Nanosheet Semiconductor Structure
Patent:
9,704,863 →
Application:
15/260,509 →
Optimized Wires for Resistance or Electromigration
Optimized Wires for Resistance or Electromigration
Method and Structure for Cut Material Selection
Patent:
9,779,944 →
Application:
15/263,959 →
Nanosheet Channel-to-Source and Drain Isolation
Patent:
9,620,590 →
Application:
15/270,109 →
Metal Fill Optimization for Self-Aligned Double Patterning
Patent:
9,735,029 →
Application:
15/273,092 →
Transistor with Air Spacer and Self-Aligned Contact
Patent:
9,721,897 →
Application:
15/276,985 →
Margin for Fin Cut Using Self-Aligned Triple Patterning
Methods and Structure to Form High K Metal Gate Stack with Single Work-Function Metal
Transistor with Improved Air Spacer
Nanosheet Mosfet with Full-Height Air-Gap Spacer
Air Gap Contact Formation for Reducing Parasitic Capacitance
Air Gap Contact Formation for Reducing Parasitic Capacitance
Forming a Contact for a Semiconductor Device
Patent:
9,917,060 →
Application:
15/331,331 →
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Fin Cut During Replacement Gate Formation
Patent:
9,741,823 →
Application:
15/336,886 →
Stable Work Function for Narrow-Pitch Devices
Stacked Transistors with Different Channel Widths
Patent:
9,660,028 →
Application:
15/339,665 →
Punch Through Stopper in Bulk Finfet Device
Fin Pitch Scaling for High Voltage Devices and Low Voltage Devices on the Same Wafer
Nanosheet Channel-to-Source and Drain Isolation
Finfet Device with Vertical Silicide on Recessed Source/Drain Epitaxy Regions
Stable Multiple Threshold Voltage Devices on Replacement Metal Gate Cmos Devices
Perpendicular Magnetic Anisotropy Free Layers with Iron Insertion and Oxide Interfaces for Spin Transfer Torque Magnetic Random Access Memory
Sram Design to Facilitate Single Fin Cut in Double Sidewall Image Transfer Process
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Patent:
9,934,970 →
Application:
15/403,371 →
Cobalt Contact and Interconnect Structures
Interconnect Structure Having Substractive Etch Feature and Damascene Feature
Memristive Device Based on Alkali-Doping of Transitional Metal Oxides
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Copper Interconnect Structure with Manganese Oxide Barrier Layer
Finfet Devices
Self-Aligned Contact Process Enabled by Low Temperature
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Hybrid Subtractive Etch/Metal Fill Process for Fabricating Interconnects
Hybrid Subtractive Etch/Metal Fill Process for Fabricating Interconnects
Nanosheet Transistors on Bulk Material
Transistor with Air Spacer and Self-Aligned Contact
Forming Insulator Fin Structure in Isolation Region to Support Gate Structures
Fin Cut During Replacement Gate Formation
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Fully Aligned via with Integrated Air Gaps
Patent:
9,966,337 →
Application:
15/459,684 →
Stacked Transistors with Different Channel Widths
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Semiconductor Fins for Finfet Devices and Sidewall Image Transfer (Sit) Processes for Manufacturing the Same
Forming a Hybrid Channel Nanosheet Semiconductor Structure
Patent:
9,892,976 →
Application:
15/465,962 →
Forming a Hybrid Channel Nanosheet Semiconductor Structure
Patent:
9,881,839 →
Application:
15/465,989 →
Methods For Removal Of Selected Nanowires In Stacked Gate All Around Architecture
Forming Gates with Varying Length Using Sidewall Image Transfer
Advanced Copper Interconnects with Hybrid Microstructure
Forming a Contact for a Semiconductor Device
Reduction of Stress in via Structure
Transistor with Air Spacer and Self-Aligned Contact
Fin Type Field Effect Transistors with Different Pitches and Substantially Uniform Fin Reveal
Two Dimension Material Fin Sidewall
Patent:
9,947,660 →
Application:
15/489,920 →
Minimizing Shorting Between Finfet Epitaxial Regions
FIN FIELD-EFFECT TRANSISTOR (FinFET) WITH REDUCED PARASITIC CAPACITANCE
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Transistor with Improved Air Spacer
Low Resistance Contact Structures for Trench Structures
Low Resistance Contact Structures for Trench Structures
Sidewall Image Transfer Nanosheet
Insulating a via in a Semiconductor Substrate
Metal Fill Optimization for Self-Aligned Double Patterning
Fin Cut During Replacement Gate Formation
Fin Density Control of Multigate Devices Through Sidewall Image Transfer Processes
Multi-Layer Filled Gate Cut to Prevent Power Rail Shorting to Gate Structure
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Stacked Nanowire Devices
Stress Retention in Fins of Fin Field-Effect Transistors
Fin Pitch Scaling for High Voltage Devices and Low Voltage Devices on the Same Wafer
Bulk Nanosheet with Dielectric Isolation
3D Bonded Semiconductor Structure with an Embedded Capacitor
Bulk Nanosheet with Dielectric Isolation
Punch Through Stopper in Bulk Finfet Device
Fin Cut Without Residual Fin Defects
Spin Transfer Torque Cell for Magnetic Random Access Memory
Structure and Method for Improved Stabilization of Cobalt Cap and/or Cobalt Liner in Interconnects
Copper Interconnect Structures
Fin Pitch Scaling for High Voltage Devices and Low Voltage Devices on the Same Wafer
Forming Insulator Fin Structure in Isolation Region to Support Gate Structures
Forming a Hybrid Channel Nanosheet Semiconductor Structure
Semiconductor Device with Different Fin Pitches
Nanosheet Transistors on Bulk Material
Patent:
9,917,152 →
Application:
15/701,894 →
Punch Through Stopper in Bulk Finfet Device
Integration of Super via Structure in Beol
Patent:
10,020,254 →
Application:
15/727,956 →
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Air Gap Spacer for Metal Gates
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Heterogeneous Source Drain Region and Extension Region
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Integration of Super via Structure in Beol
Patent:
10,020,255 →
Application:
15/798,794 →
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Two Dimension Material Fin Sidewall
Two Dimension Material Fin Sidewall
Cobalt Contact and Interconnect Structures
Silicon Nitride Fill for Pc Gap Regions to Increase Cell Density
Finfet Devices
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Stable Work Function for Narrow-Pitch Devices
Nanosheet Transistor
Patent:
10,243,061 →
Application:
15/814,376 →
Integration of Thick and Thin Nanosheet Transistors on a Single Chip
Patent:
10,229,971 →
Application:
15/815,061 →
Interconnect Structure Having Subtractive Etch Feature and Damascene Feature
Method of Forming a Three-Dimensional Bonded Semiconductor Structure Having Nitridized Oxide Regions
Homogeneous Densification of Fill Layers for Controlled Reveal of Vertical Fins
Copper Interconnect Structure with Manganese Oxide Barrier Layer
Copper Interconnect Structure with Manganese Oxide Barrier Layer
Finfet Devices
Stress Retention in Fins of Fin Field-Effect Transistors
Selective Ild Deposition for Fully Aligned via with Airgap
Finfet Gate Cut After Dummy Gate Removal
Patent:
10,229,854 →
Application:
15/841,933 →
Forming Gates with Varying Length Using Sidewall Image Transfer
Two Dimension Material Fin Sidewall
Low-Resistivity Metallic Interconnect Structures with Self-Forming Diffusion Barrier Layers
Patent:
10,204,829 →
Application:
15/870,213 →
Forming Nanosheet Transistor Using Sacrificial Spacer and Inner Spacers
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Multi-Level Metallization Interconnect Structure
Minimizing Shorting Between Finfet Epitaxial Regions
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Margin for Fin Cut Using Self-Aligned Triple Patterning
Perpendicular Magnetic Anisotropy Free Layers with Iron Insertion and Oxide Interfaces for Spin Transfer Torque Magnetic Random Access Memory
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Fin Type Field Effect Transistors with Different Pitches and Substantially Uniform Fin Reveal
Forming a Hybrid Channel Nanosheet Semiconductor Structure
Nanosheet Transistors on Bulk Material
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Finfet Devices
Finfet Devices
Spin Transfer Torque Cell for Magnetic Random Access Memory
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 10, 2019
From: NITTA, SATYA V.; PONOTH, SHOM
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 051224/0491 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Change of Name
Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →
Change of Name
Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0462 →
Change of Name
Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
Change of Name
Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0849 →