FinFET device with vertical silicide on recessed source/drain epitaxy regions
A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.
1. A semiconductor device structure comprising:
at least one fin field effect transistor including a fin structure including a channel region portion, a source region portion and a drain region portion;
a metal semiconductor alloy contact structure present directly on a sidewall of at least one of the source region portion and the drain region portion of the fin structure and present on a sidewall of epitaxial source and drain region structures; and
a gate structure present on the channel region portion of the fin structure.
2. The semiconductor device of claim 1 , wherein the metal semiconductor alloy contact structure is not present on an upper surface of said at least one of the drain region portion and the source region portion of the fin structure.
3. The semiconductor device of claim 1 , wherein the fin structure is comprised of a semiconductor material selected from the group consisting of silicon, silicon germanium and combinations thereof.
4. The semiconductor device of claim 1 , wherein the metal semiconductor alloy contact structure is a silicide.
5. The semiconductor device of claim 1 , wherein the metal semiconductor alloy is selected from the group consisting of nickel silicide, tungsten silicide, cobalt silicide, platinum silicide, and combinations thereof.
6. The semiconductor device of claim 1 , wherein the metal semiconductor alloy contact is not present on an upper surface of the fin structure, and is not present on an upper surface of the epitaxial source and drain region structures.
7. The semiconductor device of claim 1 , wherein the metal semiconductor alloy contact have a height ranging from 25 nm to 220 nm.
8. A semiconductor device structure comprising:
at least one fin field effect transistor including a fin structure including a channel region portion, a source region portion and a drain region portion;
a metal semiconductor alloy contact structure present directly on a sidewall of at least one of the source region portion and the drain region portion of the fin structure and present on a sidewall of epitaxial source and drain region structures, wherein the metal semiconductor alloy contact structure is not present on an upper surface of said at least one of the drain region portion and the source region portion of the fin structure; and
a gate structure present on the channel region portion of the fin structure.
9. The semiconductor device of claim 8 , wherein the fin structure is comprised of a semiconductor material selected from the group consisting of silicon, silicon germanium and combinations thereof.
10. The semiconductor device of claim 8 , wherein the metal semiconductor alloy contact structure is a silicide.
11. The semiconductor device of claim 8 , wherein the metal semiconductor alloy is selected from the group consisting of nickel silicide, tungsten silicide, cobalt silicide, platinum silicide, and combinations thereof.
12. The semiconductor device of claim 8 , wherein the metal semiconductor alloy contact is not present on an upper surface of the fin structure, and is not present on an upper surface of the epitaxial source and drain region structures.
13. The semiconductor device of claim 8 , wherein the metal semiconductor alloy contact have a height ranging from 25 nm to 220 nm.
14. A semiconductor device structure comprising:
at least one fin field effect transistor including a fin structure including a channel region portion, a source region portion and a drain region portion; and
a metal semiconductor alloy contact structure present directly on a sidewall of at least one of the source region portion and the drain region portion of the fin structure and present on a sidewall of epitaxial source and drain region structures.
15. The semiconductor device of claim 14 , wherein the metal semiconductor alloy contact structure is not present on an upper surface of said at least one of the drain region portion and the source region portion of the fin structure.
16. The semiconductor device of claim 14 , wherein the fin structure is comprised of a semiconductor material selected from the group consisting of silicon, silicon germanium and combinations thereof.
17. The semiconductor device of claim 14 , wherein the metal semiconductor alloy contact structure is a silicide.
18. The semiconductor device of claim 14 , wherein the metal semiconductor alloy is selected from the group consisting of nickel silicide, tungsten silicide, cobalt silicide, platinum silicide, and combinations thereof.
19. The semiconductor device of claim 14 , wherein the metal semiconductor alloy contact is not present on an upper surface of the fin structure, and is not present on an upper surface of the epitaxial source and drain region structures.
20. The semiconductor device of claim 14 , wherein the metal semiconductor alloy contact have a height ranging from 25 nm to 220 nm.