Self-aligned contact process enabled by low temperature
View Patent ↗Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.
1. A method of forming self-aligned contacts for a semiconductor device, the method comprising:
forming a metal gate structure on a portion of a semiconductor layer of a substrate and contacting inner sidewalls of a gate spacer;
forming a second sacrificial epitaxial layer on a first sacrificial epitaxial layer, wherein the first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer;
recessing the first and second sacrificial epitaxial layers, the recessing exposing at least a portion of the source/drain regions;
forming a first dielectric layer on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure;
forming at least one cavity within the first dielectric layer above at least a portion of one or more of the source/drain regions; and
forming at least one metal contact within the at least one cavity.
2. The method of claim 1 , wherein prior to forming the metal gate structure the method comprises:
forming a replacement gate structure on the portion of the semiconductor layer;
forming the gate spacer on the replacement gate structure;
forming the first sacrificial epitaxial layer on the source/drain regions, wherein forming the first sacrificial epitaxial layer creates a cavity between the first sacrificial epitaxial layer and an outer sidewall of the gate spacer; and
forming a second dielectric layer within the cavity between the first sacrificial epitaxial layer and the outer sidewall of the gate spacer.
3. The method of claim 2 , wherein forming the metal gate structure comprises:
removing the replacement gate structure, the removing exposing the portion of the semiconductor layer; and
forming a dielectric spacer on the exposed portion of the semiconductor layer; and
forming a gate conductor within the cavity in contact with the dielectric spacer.
4. The method of claim 1 , wherein the portion of the semiconductor layer comprises a fin structure.
5. The method of claim 1 , further comprising:
forming the first sacrificial epitaxial layer at a first temperature; and
forming the second sacrificial epitaxial layer at a second temperature, wherein the first temperature is higher than the second temperature.
6. The method of claim 1 , further comprising:
forming a third dielectric layer between and in contact with a first inner sidewall of the second sacrificial epitaxial layer and a second inner sidewall of the second sacrificial epitaxial layer, wherein the third dielectric layer is further formed above and in contact with the metal gate structure.
7. The method of claim 6 , wherein the at least one cavity exposes at least a portion of the third dielectric layer, and wherein the at least one metal contact is further formed on the portion of the third dielectric layer.
8. A method of forming self-aligned contacts for a semiconductor device, the method comprising:
forming a metal gate structure on a portion of the semiconductor layer of a substrate and contacting inner sidewalls of a gate spacer;
forming a second epitaxial layer on a first sacrificial epitaxial layer, wherein the first epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer;
forming a first dielectric layer on a top surface of the second epitaxial layer;
recessing at least a portion of the first dielectric layer, the second epitaxial layer, and the first epitaxial layer, the recessing forming at one least cavity exposing at least a portion of at least one of the source/drain regions; and
forming at least one metal contact within the at least one cavity.
9. The method of claim 8 , wherein prior to forming the metal gate structure the method comprises:
forming a replacement gate structure on the portion of the semiconductor layer;
forming the gate spacer on the replacement gate structure;
forming the first epitaxial layer on the source/drain regions, wherein forming the first epitaxial layer creates a cavity between the first epitaxial layer and an outer sidewall of the gate spacer; and
forming a second dielectric layer within the cavity between the first epitaxial layer and the outer sidewall of the gate spacer.
10. The method of claim 9 , wherein forming the metal gate structure comprises:
removing the replacement gate structure, the removing exposing the portion of the semiconductor layer; and
forming a dielectric spacer on the exposed portion of the semiconductor layer; and
forming a gate conductor within the cavity in contact with the dielectric spacer.
11. The method of claim 8 , wherein the portion of the semiconductor layer comprises a fin structure.
12. The method of claim 8 , further comprising:
forming the first epitaxial layer at a first temperature; and
forming the second epitaxial layer at a second temperature, wherein the first temperature is higher than the second temperature.
13. The method of claim 8 , further comprising:
prior to the first dielectric layer being formed, forming a second dielectric layer between and in contact with a first inner sidewall of the second epitaxial layer and a second inner sidewall of the second epitaxial layer, wherein the third dielectric layer is further formed above and in contact with the metal gate structure.
14. The method of claim 8 , wherein the at least one cavity exposes at least a portion of the second dielectric layer, and wherein the at least one metal contact is further formed on the portion of the second dielectric layer.
15. A semiconductor device comprising:
a substrate;
a semiconductor layer formed on the substrate;
a metal gate structure formed on a portion of the semiconductor layer;
a gate spacer formed on the metal gate structure;
a first epitaxial layer formed on source/drain regions of the semiconductor layer and adjacent to the gate spacer;
a second epitaxial layer formed on a top surface of the first epitaxial layer, wherein at least a portion of the second epitaxial layer is formed above of the metal gate structure; and
at least one self-aligned metal contact formed on at least one of the source/drain regions; and
a dielectric layer formed between and in contact with a first inner sidewall of the second epitaxial layer and a second inner sidewall of the second epitaxial layer, wherein the dielectric layer is further formed above and in contact with the metal gate structure.
16. The semiconductor device of claim 15 , wherein the at least one metal contact is in contact with at least a sidewall and a portion of a top surface of the dielectric layer.
17. The semiconductor device of claim 15 , further comprising:
a dielectric layer formed between and in contact with an inner sidewall of the first epitaxial layer and an outer sidewall of the gate spacer.
18. The semiconductor device of claim 15 , further comprising:
a dielectric layer formed on a top surface of the second epitaxial layer.
19. The semiconductor device of claim 18 , wherein the at least one metal contact is in contact with at least a sidewall of the dielectric layer.