IP Library Granted Patent US 10,224,241
Granted Patent B2
US 10,224,241 · App. 15/825,889 · Granted Mar 5, 2019

Copper interconnect structure with manganese oxide barrier layer

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Quick Facts
Patent No.
US 10,224,241
App. No.
15/825,889
Granted
Mar 5, 2019
Kind
B2
Abstract

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Claims (38)

1. A method, comprising:

forming a copper based interconnect structure comprising:

forming a first barrier layer coating sidewalls and a bottom of an opening of a dielectric material;

forming an Mn-containing layer on the first barrier layer; and

forming a copper layer on the Mn-containing layer;

forming a capping layer on the copper based interconnect structure, wherein the forming the capping layer creates a residual material on a surface of the dielectric material;

forming a second barrier layer on the capping layer by outdiffusing Mn from the Mn-containing layer to a surface of the capping layer; and

removing the residual material, while the second barrier layer on the surface of the capping layer protects the capping layer.

2. The method of claim 1 , wherein the forming the second barrier layer comprises outdiffusing Mn to the surface of the capping layer during an anneal process.

3. The method of claim 1 , wherein the forming the second barrier layer comprises outdiffusing Mn from the Mn-containing layer through both the copper layer and the capping layer during an anneal process.

4. The method of claim 3 , wherein:

a bottom surface of the capping layer is on an upper surface of the copper layer; and

the second barrier layer is on an upper surface and side surfaces of the capping layer.

5. The method of claim 4 , wherein the capping layer is composed of cobalt (Co), and further comprising oxidizing the capping layer and the residual material, the oxidizing forming a first cobalt oxide (CoO) passivation layer on the capping layer and a second CoO passivation layer on the residual material.

6. The method of claim 1 , further comprising performing a chemical mechanical polish on a top surface of the copper based interconnect structure and a top surface of the dielectric material prior to the forming the capping layer on the copper based interconnect structure.

7. The method of claim 1 , wherein the capping layer extends entirely across a top surface of the copper based interconnect structure.

8. The method of claim 1 , wherein the capping layer comprises cobalt or CoWP.

9. The method of claim 1 , wherein the first barrier layer comprises one of TaN and cobalt.

10. A method, comprising:

forming a copper based interconnect structure in a dielectric material, wherein the copper based interconnect structure comprises a copper layer and an Mn-containing layer;

forming a capping layer on the copper layer, wherein the forming the capping layer creates a residual material on a surface of the dielectric material;

forming a barrier layer on the capping layer by outdiffusing Mn from the Mn-containing layer to a surface of the capping layer; and

removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

11. The method of claim 10 , wherein the forming the barrier layer comprises outdiffusing Mn to the surface of the capping layer during an anneal process.

12. The method of claim 10 , wherein the forming the barrier layer comprises outdiffusing Mn from the Mn-containing layer through both the copper layer and the capping layer during an anneal process.

13. The method of claim 12 , wherein:

a bottom surface of the capping layer is on an upper surface of the copper layer; and

the barrier layer is on an upper surface and side surfaces of the capping layer.

14. The method of claim 10 , further comprising performing a chemical mechanical polish on a top surface of the copper based interconnect structure and a top surface of the dielectric material prior to the forming the capping layer on the copper based interconnect structure.

15. The method of claim 10 , wherein the capping layer extends entirely across a top surface of the copper based interconnect structure.

16. The method of claim 10 , wherein the capping layer comprises cobalt or CoWP.

17. The method of claim 10 , wherein the barrier layer is formed on a top surface and side surfaces of the capping layer.

18. A method, comprising:

forming a capping layer on a copper layer, wherein the forming the capping layer creates a residual material on a surface of a dielectric material;

forming a barrier layer on the capping layer by outdiffusing Mn from an underlying Mn-containing layer, through both the copper layer and the capping layer, to at least one surface of the capping layer during an anneal process; and

removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

19. The method of claim 18 , further comprising performing a chemical mechanical polish on a top surface of the copper layer and a top surface of the dielectric material prior to the forming the capping layer on the copper layer.

20. The method of claim 18 , wherein the at least one surface of the capping layer comprises a top surface and side surfaces of the capping layer such that the barrier layer is formed on the top surface and the side surfaces of the capping layer.

Assignments (5)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0410 →
CERTIFICATE OF CONVERSION & CHANGE OF NAME Recorded Sep 7, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 061388/0199 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2017
From: EDELSTEIN, DANIEL C.; NGUYEN, SON V.; NOGAMI, TAKESHI; PRIYADARSHINI, DEEPIKA; SHOBHA, HOSADURGA K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044251/0898 →
Cited By (1)
US 12,685,112