IP Library Assignment 061388/0199
Patent Assignment
Reel/Frame 061388/0199

Certificate of Conversion & Change of Name

Recorded: 2022-09-07 Pages: 8
Assignor
TESSERA, INC.
Executed: 2021-10-01
Assignee
TESSERA LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties (89)
Semiconductor Device with Reduced via Resistance
Patent: 9,349,691 →
Application: 14/339,704 →
Publication: US 2016/0027738
Interconnect Structure with Capping Layer and Barrier Layer
Patent: 9,455,182 →
Application: 14/466,539 →
Publication: US 2016/0056076
Minimizing Shorting Between Finfet Epitaxial Regions
Patent: 9,443,853 →
Application: 14/680,099 →
Finfet Devices
Patent: 9,685,507 →
Application: 14/750,013 →
Publication: US 2016/0379892
Stackable Molded Microelectronic Packages with Area Array Unit Connectors
Patent: 9,553,076 →
Application: 14/878,548 →
Publication: US 2016/0086922
Interconnect Structure with Barrier Layer
Patent: 9,601,371 →
Application: 14/882,568 →
Publication: US 2016/0056112
Advanced Copper Interconnects with Hybrid Microstructure
Patent: 9,799,605 →
Application: 14/952,017 →
Publication: US 2017/0148738
Sram Design to Facilitate Single Fin Cut in Double Sidewall Image Transfer Process
Patent: 9,564,446 →
Application: 14/971,212 →
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Patent: 9,601,514 →
Application: 15/006,284 →
Nanowire with Sacrificial Top Wire
Application: 15/045,759 →
Publication: US 2017/0236900
Semiconductor Device with Reduced via Resistance
Patent: 9,859,160 →
Application: 15/070,411 →
Publication: US 2016/0197010
Semiconductor Device with Reduced via Resistance
Patent: 9,953,869 →
Application: 15/078,066 →
Publication: US 2016/0204069
Semiconductor Interconnect Structure with Double Conductors
Patent: 9,837,350 →
Application: 15/097,033 →
Publication: US 2017/0294381
Finfet Devices
Application: 15/182,043 →
Publication: US 2016/0380051
Finfet Devices
Patent: 9,613,869 →
Application: 15/182,048 →
Publication: US 2016/0379887
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Patent: 9,997,451 →
Application: 15/199,321 →
Publication: US 2018/0005941
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Patent: 9,768,072 →
Application: 15/199,352 →
Minimizing Shorting Between Finfet Epitaxial Regions
Patent: 9,704,753 →
Application: 15/203,847 →
Publication: US 2016/0315144
Interconnect Structure
Patent: 9,947,581 →
Application: 15/214,760 →
Publication: US 2016/0329279
Selective Recessing to Form a Fully Aligned Via
Application: 15/229,470 →
Publication: US 2018/0040510
Minimizing Shorting Between Finfet Epitaxial Regions
Patent: 9,852,951 →
Application: 15/237,802 →
Publication: US 2016/0358824
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Patent: 9,716,046 →
Application: 15/254,573 →
Publication: US 2017/0213772
Nanosheet Channel-to-Source and Drain Isolation
Patent: 9,620,590 →
Application: 15/270,109 →
Forming a Sacrificial Liner for Dual Channel Devices
Patent: 9,773,893 →
Application: 15/276,029 →
Nanosheet Channel-to-Source and Drain Isolation
Application: 15/355,521 →
Publication: US 2018/0083118
Forming a Sacrificial Liner for Dual Channel Devices
Application: 15/395,637 →
Publication: US 2018/0090604
Sram Design to Facilitate Single Fin Cut in Double Sidewall Image Transfer Process
Application: 15/396,993 →
Publication: US 2017/0178963
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Patent: 9,934,970 →
Application: 15/403,371 →
Copper Interconnect Structure with Manganese Oxide Barrier Layer
Patent: 9,947,579 →
Application: 15/417,390 →
Publication: US 2017/0140981
Finfet Devices
Application: 15/417,597 →
Publication: US 2017/0140995
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Application: 15/425,158 →
Publication: US 2018/0005899
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Application: 15/464,817 →
Publication: US 2017/0213730
Advanced Copper Interconnects with Hybrid Microstructure
Application: 15/470,038 →
Publication: US 2017/0200643
Minimizing Shorting Between Finfet Epitaxial Regions
Patent: 9,985,024 →
Application: 15/494,586 →
Publication: US 2017/0229455
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Patent: 9,985,117 →
Application: 15/588,969 →
Publication: US 2017/0243959
Semiconductor Interconnect Structure with Double Conductors
Application: 15/609,672 →
Publication: US 2017/0294382
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Application: 15/627,927 →
Publication: US 2018/0005900
Forming a Sacrificial Liner for Dual Channel Devices
Application: 15/629,280 →
Publication: US 2018/0090606
Forming a Sacrificial Liner for Dual Channel Devices
Application: 15/652,888 →
Publication: US 2018/0090599
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Application: 15/786,090 →
Publication: US 2018/0197738
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Application: 15/798,886 →
Publication: US 2018/0068901
Finfet Devices
Application: 15/813,277 →
Publication: US 2018/0076094
Nanosheet Transistor
Application: 15/814,376 →
Copper Interconnect Structure with Manganese Oxide Barrier Layer
Application: 15/825,646 →
Publication: US 2018/0090371
Copper Interconnect Structure with Manganese Oxide Barrier Layer
Application: 15/825,889 →
Publication: US 2018/0082894
Finfet Devices
Application: 15/827,053 →
Publication: US 2018/0090567
Selective Ild Deposition for Fully Aligned via with Airgap
Application: 15/837,361 →
Publication: US 2019/0181033
Two-Color Self-Aligned Double Patterning (Sadp) to Yield Static Random Access Memory (Sram) and Dense Logic
Application: 15/842,841 →
Publication: US 2019/0189457
Forming Nanosheet Transistor Using Sacrificial Spacer and Inner Spacers
Application: 15/880,757 →
Publication: US 2019/0237559
Semiconductor Device with Reduced via Resistance
Application: 15/897,526 →
Publication: US 2018/0174903
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Application: 15/908,377 →
Publication: US 2018/0190585
Minimizing Shorting Between Finfet Epitaxial Regions
Application: 15/923,097 →
Publication: US 2018/0204837
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Application: 15/928,563 →
Publication: US 2018/0226497
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Application: 15/976,226 →
Publication: US 2018/0261513
Selective Recessing to Form a Fully Aligned Via
Application: 16/014,020 →
Publication: US 2018/0315653
Selective Recessing to Form a Fully Aligned Via
Application: 16/014,025 →
Publication: US 2018/0315654
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Application: 16/014,676 →
Publication: US 2018/0315841
Nanowire with Sacrificial Top Wire
Application: 16/042,388 →
Publication: US 2018/0331180
Field effect transistor structures
Application: 16/042,498 →
Publication: US 2018/0350909
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Application: 16/049,442 →
Publication: US 2018/0366408
Advanced Copper Interconnects with Hybrid Microstructure
Application: 16/057,056 →
Publication: US 2018/0342419
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Application: 16/058,232 →
Publication: US 2018/0350599
Nanosheet Channel-to-Source and Drain Isolation
Application: 16/106,359 →
Publication: US 2018/0374930
Finfet Devices
Application: 16/115,953 →
Publication: US 2018/0374756
Finfet Devices
Application: 16/115,967 →
Publication: US 2019/0013247
Interconnect Structure
Application: 16/118,998 →
Publication: US 2018/0374748
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Application: 16/227,733 →
Publication: US 2019/0131179
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Application: 16/234,974 →
Publication: US 2019/0139832
Nanosheet Transistor
Application: 16/252,663 →
Publication: US 2019/0157420
Finfet Devices
Application: 16/265,110 →
Publication: US 2019/0181049
Minimizing Shorting Between Finfet Epitaxial Regions
Application: 16/296,433 →
Publication: US 2019/0206865
Forming Nanosheet Transistor Using Sacrificial Spacer and Inner Spacers
Application: 16/391,622 →
Publication: US 2019/0252516
Selective Ild Deposition for Fully Aligned via with Airgap
Application: 16/406,115 →
Publication: US 2019/0267278
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Application: 16/421,587 →
Publication: US 2019/0279931
Interconnect Structure
Application: 16/657,169 →
Publication: US 2020/0051854
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Application: 16/675,630 →
Publication: US 2020/0075336
Forming a Sacrificial Liner for Dual Channel Devices
Application: 16/685,229 →
Publication: US 2020/0083364
Forming a Sacrificial Liner for Dual Channel Devices
Application: 16/685,329 →
Publication: US 2020/0091336
Semiconductor Device with Reduced via Resistance
Application: 16/689,142 →
Publication: US 2020/0090993
Semiconductor Device with Reduced via Resistance
Application: 16/689,223 →
Publication: US 2020/0090994
Two-Color Self-Aligned Double Patterning (Sadp) to Yield Static Random Access Memory (Sram) and Dense Logic
Application: 16/796,614 →
Publication: US 2020/0266072
Nanosheet Channel-to-Source and Drain Isolation
Application: 16/798,079 →
Publication: US 2020/0266284
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Application: 16/817,491 →
Publication: US 2020/0388568
Advanced Copper Interconnects with Hybrid Microstructure
Application: 16/835,056 →
Publication: US 2020/0227317
Selective Ild Deposition for Fully Aligned via with Airgap
Application: 16/868,475 →
Publication: US 2020/0388525
Finfet Devices
Application: 16/911,158 →
Publication: US 2020/0328124
Nanosheet Transistor
Application: 16/939,415 →
Publication: US 2020/0357895
Copper Interconnect Structure with Manganese Barrier Layer
Application: 17/011,823 →
Publication: US 2020/0402848
Selective Recessing to Form a Fully Aligned Via
Application: 17/093,351 →
Publication: US 2021/0082758
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 22, 2014
From: EDELSTEIN, DANIEL C.; NGUYEN, SON V.; NOGAMI, TAKESHI; PRIYADARSHINI, DEEPIKA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 033594/0456 →
Assignment of Assignor's Interest Apr 7, 2015
From: CHENG, KANGGUO; PRANATHARTHIHARAN, BALASUBRAMANIAN; REZNICEK, ALEXANDER; SURISETTY, CHARAN V.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 035344/0341 →
Assignment of Assignor's Interest Jun 25, 2015
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; STANDAERT, THEODORUS E.; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 035907/0494 →
Assignment of Assignor's Interest Oct 14, 2015
From: EDELSTEIN, DANIEL C.; NGUYEN, SON V.; NOGAMI, TAKESHI; PRIYADARSHINI, DEEPIKA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036793/0890 →
Assignment of Assignor's Interest Oct 14, 2015
From: HABA, BELGACEM
To: TESSERA RESEARCH LLC
Reel/Frame 036791/0098 →
Assignment of Assignor's Interest Oct 15, 2015
From: TESSERA RESEARCH LLC
To: TESSERA, INC.
Reel/Frame 036800/0979 →
Assignment of Assignor's Interest Nov 25, 2015
From: EDELSTEIN, DANIEL C.; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037141/0033 →
Assignment of Assignor's Interest Jan 5, 2016
From: WEYBRIGHT, MARY E.; WONG, ROBERT C.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037409/0288 →
Assignment of Assignor's Interest Jan 26, 2016
From: CHENG, KANGGUO; LI, JUNTAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037582/0352 →
Assignment of Assignor's Interest Feb 17, 2016
From: CHANG, JOSEPHINE B.; DORIS, BRUCE B.; GUILLORN, MICHAEL A.; LAUER, ISAAC
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037754/0509 →
Assignment of Assignor's Interest Mar 15, 2016
From: MURRAY, CONAL E.; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037982/0799 →
Assignment of Assignor's Interest Mar 23, 2016
From: MURRAY, CONAL E.; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038079/0159 →
Assignment of Assignor's Interest Apr 12, 2016
From: BRIGGS, BENJAMIN D.; NOGAMI, TAKESHI; PATLOLLA, RAGHUVEER R.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038258/0383 →
Assignment of Assignor's Interest Jun 14, 2016
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; STANDAERT, THEODORUS E.; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038911/0710 →
Assignment of Assignor's Interest Jun 14, 2016
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; STANDAERT, THEODORUS E.; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038911/0733 →
Assignment of Assignor's Interest Jun 30, 2016
From: CHENG, KANGGUO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039059/0717 →
Assignment of Assignor's Interest Jul 8, 2016
From: BRIGGS, BENJAMIN DAVID; CLEVENGER, LAWRENCE A.; DEPROSPO, BARTLET H.; HUANG, HUAI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039110/0300 →
Security Interest Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Assignment of Assignor's Interest Nov 15, 2017
From: CHENG, KANGGUO; LI, JUNTAO; WU, HENG; XU, PENG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044140/0537 →
Assignment of Assignor's Interest Nov 15, 2017
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; STANDAERT, THEODORUS E.; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044130/0081 →
Assignment of Assignor's Interest Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
Assignment of Assignor's Interest Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
Security Interest Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0410 →