Forming a sacrificial liner for dual channel devices
Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.
1. A method of forming a semiconductor device, comprising:
forming a liner over one or more channel fins on a substrate;
etching down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins;
filling an area around the one or more channel fins and substrate fins with a flowable dielectric; and
annealing the flowable dielectric to solidify the flowable dielectric, wherein the anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the portion where the sidewalls are oxidized than in a portion covered by the liner.
2. The method of claim 1 , further comprising forming a plurality of channel fins from two distinct channel materials.
3. The method of claim 2 , wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.
4. The method of claim 1 , wherein etching down into the substrate forms a substrate cap underneath the channel fin on a top surface of the remaining substrate material.
5. The method of claim 1 , further comprising recessing the solidified dielectric to a level below a top level of the liner and above a bottom level of the liner.
6. The method of claim 1 , further comprising etching away the liner to expose the one or more channel fins and divots at sidewalls of the one or more channel fins.
7. The method of claim 6 , further comprising:
depositing a gate dielectric layer over the one or more channel fins and in the divots; and
depositing a gate over the gate dielectric layer.
8. The method of claim 1 , wherein the liner is formed from silicon nitride.
9. The method of claim 1 , further comprising forming the one or more channel fins with an etch that partially etches the substrate.
10. A method of forming a semiconductor device, comprising:
forming a liner over one or more channel fins on a substrate;
etching down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins and a substrate cap underneath the channel fin on a top surface of remaining substrate material;
filling an area around the one or more channel fins and substrate fins with a flowable dielectric;
annealing the flowable dielectric to solidify the flowable dielectric, wherein the anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the portion where the sidewalls are oxidized than in a portion covered by the liner; and
recessing the solidified dielectric to a level below a top level of the liner and above a bottom level of the liner.
11. The method of claim 10 , further comprising forming a plurality of channel fins from two distinct channel materials.
12. The method of claim 11 , wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.
13. The method of claim 10 , further comprising forming the one or more channel fins with an etch that partially etches the substrate.
14. The method of claim 10 , further comprising etching away the liner to expose the one or more channel fins and divots at sidewalls of the one or more channel fins.
15. The method of claim 14 , further comprising:
depositing a gate dielectric layer over the one or more channel fins and in the divots; and
depositing a gate over the gate dielectric layer.
16. The method of claim 10 , wherein the liner is formed from silicon nitride.
17. A method of forming a semiconductor device, comprising:
forming one or more channel fins on a substrate with an etch that partially etches the substrate;
forming a liner over the one or more channel fins;
etching down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins and a substrate cap underneath the channel fin on a top surface of remaining substrate material;
filling an area around the one or more channel fins and substrate fins with a flowable dielectric;
annealing the flowable dielectric to solidify the flowable dielectric, wherein the anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the portion where the sidewalls are oxidized than in a portion covered by the liner;
recessing the solidified dielectric to a level below a top level of the liner and above a bottom level of the liner;
etching away the liner to expose the one or more channel fins and divots at sidewalls of the one or more channel fins;
depositing a gate dielectric layer over the one or more channel fins and in the divots; and
depositing a gate over the gate dielectric layer.
18. The method of claim 17 , further comprising forming a plurality of channel fins from two distinct channel materials.
19. The method of claim 18 , wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.
20. The method of claim 17 , wherein the liner is formed from silicon nitride.