Forming nanosheet transistor using sacrificial spacer and inner spacers
Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
1. A nanosheet transistor device comprising:
first and second adjacent nanosheet structures, each nanosheet structure comprising:
a plurality of vertically arranged nanosheet layers, each nanosheet layer of the plurality of vertically arranged nanosheet layers comprising a silicon nanosheet, the plurality of vertically arranged nanosheet layers separated from each other by a gate material, the gate material forming a gate structure above, below, and around each nanosheet layer of the plurality of vertically arranged nanosheet layers;
a plurality of inner spacer pairs, each inner spacer pair underlying a nanosheet layer; and
a pair of upper spacers, each upper spacer overlying an uppermost nanosheet layer and extending vertically beside an uppermost region of gate material; and
an epitaxial source/drain structure shared by the first and second adjacent nanosheet structures, the epitaxial source/drain structure contacting (i) each of the vertically arranged nanosheet layers of the plurality of vertically arranged nanosheet layers and (ii) each of the inner spacers of the first and second adjacent nanosheet structures,
wherein (i) the pair of upper spacers and (ii) the plurality of inner spacer pairs of each nanosheet structure of the first and second adjacent nanosheet structures separate a gate structure of that nanosheet structure from the epitaxial source/drain structure, and
wherein (i) the pair of upper spacers and (ii) the plurality of inner spacer pairs extend laterally past an outer edge of the vertically arranged nanosheet layers.
2. The nanosheet transistor device of claim 1 , wherein the plurality of inner pairs comprises a low-K dielectric material.
3. The nanosheet transistor device of claim 1 , wherein the plurality of inner pairs comprises SiBCN.
4. The nanosheet transistor device of claim 1 , wherein the first and second adjacent nanosheet structures are disposed upon a dielectric layer upon a substrate.
5. The nanosheet transistor device of claim 1 , wherein the epitaxial source/drain structure comprises SiGe.
6. The nanosheet transistor device of claim 1 , wherein the epitaxial source/drain structure comprises phosphorous-doped silicon.
7. A nanosheet transistor device comprising:
first and second adjacent nanosheet structures, each nanosheet structure comprising:
a plurality of vertically arranged nanosheet layers, each nanosheet layer of the plurality of vertically arranged nanosheet layers comprising a silicon nanosheet, the plurality of vertically arranged nanosheet layers separated from each other by a gate material, the gate material forming a gate structure above, below, and around each nanosheet layer;
a plurality of inner spacer pairs, each inner spacer pair underlying a nanosheet layer; and
a pair of upper spacers, each upper spacer overlying an uppermost nanosheet layer and extending vertically beside an uppermost region of gate material; and
an epitaxial source/drain structure shared by the first and second adjacent nanosheet structures, the epitaxial source/drain structure contacting (i) each of the nanosheet layers and (ii) each of the inner spacers of the first and second adjacent nanosheet structures,
wherein (i) the pair of upper spacers and (ii) the plurality of inner spacer pairs of each nanosheet structure of the first and second adjacent nanosheet structures separate a gate structure of that nanosheet structure from the epitaxial source/drain structure, and
wherein (i) the pair of upper spacers and (ii) the plurality of inner spacer pairs of each nanosheet structure of the first and second adjacent nanosheet structures are recessed into the epitaxial source/drain structure.
8. The nanosheet transistor device of claim 7 , wherein the plurality of inner spacer pairs comprise a low-K dielectric material.
9. The nanosheet transistor device of claim 7 , wherein the first and second adjacent nanosheet structures are disposed upon a dielectric layer upon a substrate.
10. The nanosheet transistor device of claim 1 , wherein the plurality of inner spacer pairs comprises boron.
11. The nanosheet transistor device of claim 1 , wherein the plurality of inner spacer pairs comprises carbon.
12. The nanosheet transistor device of claim 1 , wherein the plurality of inner spacer pairs and the pair of upper spacers comprise the same material.
13. The nanosheet transistor device of claim 1 , further comprising a cap upon the uppermost region of gate material, the pair of upper spacers extending vertically beside the cap.
14. The nanosheet transistor device of claim 7 , wherein the plurality of inner spacer pairs comprises SiBCN.
15. The nanosheet transistor device of claim 7 , wherein the epitaxial source/drain structure comprises SiGe.
16. The nanosheet transistor device of claim 7 , wherein the epitaxial source/drain structure comprises phosphorous-doped silicon.
17. The nanosheet transistor device of claim 7 , wherein the plurality of inner spacer pairs comprises boron.
18. The nanosheet transistor device of claim 7 , wherein the plurality of inner spacer pairs comprises carbon.
19. The nanosheet transistor device of claim 7 , wherein the plurality of inner spacer pairs and the pair of upper spacers comprise the same material.
20. The nanosheet transistor device of claim 7 , further comprising a cap upon the uppermost region of gate material, the pair of upper spacers extending vertically beside the cap.