Patent Assignment
Reel/Frame 051489/0324
Assignment of Assignor's Interest
Recorded: 2020-01-06
Pages: 17
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2019-12-27
Assignee
TESSERA, INC.
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(82)
Interconnect Structures Incorporating Air-Gap Spacers
Application:
11/855,211 →
Publication:
US 2009/0072409
Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers
Application:
11/855,280 →
Publication:
US 2009/0075470
Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers
Application:
13/096,757 →
Publication:
US 2011/0237075
Hybrid Bonding Techniques for Multi-Layer Semiconductor Stacks
Application:
13/618,656 →
Publication:
US 2013/0011968
Iii-V Semiconductor Devices with Selective Oxidation
Application:
14/547,181 →
Publication:
US 2016/0141360
Hybrid Subtractive Etch/Metal Fill Process for Fabricating Interconnects
Application:
14/817,783 →
Publication:
US 2017/0040257
Sti Region for Small Fin Pitch in Finfet Devices
Application:
14/828,551 →
Publication:
US 2015/0357328
Stable Work Function for Narrow-Pitch Devices
Application:
15/222,151 →
Publication:
US 2017/0148890
Low Resistance Contact Structures Including a Copper Fill for Trench Structures
Application:
15/345,574 →
Publication:
US 2017/0117181
Air Gap Spacer for Metal Gates
Selective Removal of Semiconductor Fins
Semiconductor Interconnect Structure with Double Conductors
Forming a Sacrificial Liner for Dual Channel Devices
Nanosheet Field Effect Transistors with Partial Inside Spacers
Two-Color Self-Aligned Double Patterning (Sadp) to Yield Static Random Access Memory (Sram) and Dense Logic
Reduction of Stress in via Structure
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Semiconductor Device with Reduced via Resistance
Low Resistance Contact Structures for Trench Structures
Application:
16/000,371 →
Publication:
US 2018/0286958
Selective Gas Etching for Self-Aligned Pattern Transfer
Low Resistance Contact Structures for Trench Structures
Application:
16/002,479 →
Publication:
US 2018/0294339
Air Gap Spacer for Metal Gates
Selective Recessing to Form a Fully Aligned Via
Selective Recessing to Form a Fully Aligned Via
Method and Structure for Forming Dielectric Isolated Finfet with Improved Source/Drain Epitaxy
Self-Aligned Contact Process Enabled by Low Temperature
Method of Fabricating Semiconductor Fins by Enhancing Oxidation of Sacrificial Mandrels Sidewalls through Angled Ion Beam Exposure
Nanowire with Sacrificial Top Wire
Field effect transistor structures
Two Dimension Material Fin Sidewall
Efficient Metal-Insulator-Metal Capacitor
Two Dimension Material Fin Sidewall
Gate Cut with Integrated Etch Stop Layer
Gate Cut with Integrated Etch Stop Layer
Punch Through Stopper in Bulk Finfet Device
Advanced Copper Interconnects with Hybrid Microstructure
Alternating Hardmasks for Tight-Pitch Line Formation
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Sidewall Image Transfer Nanosheet
Nanosheet Channel-to-Source and Drain Isolation
Stacked Transistors with Different Channel Widths
Interconnect Structure
Low-Resistivity Metallic Interconnect Structures with Self-Forming Diffusion Barrier Layers
Application:
16/213,618 →
Publication:
US 2019/0221477
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Fabrication of a Vertical Fin Field Effect Transistor with Reduced Dimensional Variations
Uniform Fin Dimensions Using Fin Cut Hardmask
Finfet Gate Cut After Dummy Gate Removal
Low Aspect Ratio Interconnect
Self-Forming Barrier for Use in Air Gap Formation
Nanosheet Transistor
Forming Self-Aligned Vias and Air-Gaps in Semiconductor Fabrication
Middle-Of-Line (Mol) Capacitance Reduction for Self-Aligned Contact in Gate Stack
Finfet Devices
Reduced Resistance Source and Drain Extensions in Vertical Field Effect Transistors
Minimizing Shorting Between Finfet Epitaxial Regions
Reduction of Stress in via Structure
Application:
16/352,946 →
Publication:
US 2019/0214339
Forming Nanosheet Transistor Using Sacrificial Spacer and Inner Spacers
Semiconductor Structures Including Middle-of-Line (Mol) Capacitance Reduction for Self-Aligned Contact in Gate Stack
Iii-V Semiconductor Devices with Selective Oxidation
Selective Ild Deposition for Fully Aligned via with Airgap
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Asymmetric High-K Dielectric for Reducing Gate Induced Drain Leakage
Bulk Nanosheet with Dielectric Isolation
High K Metal Gate Stack with Single Work-Function Metal
Application:
16/454,178 →
Publication:
US 2019/0318966
Self Aligned Replacement Metal Source/Drain Finfet
Homogeneous Densification of Fill Layers for Controlled Reveal of Vertical Fins
Alternating Hardmasks for Tight-Pitch Line Formation
Interconnect Structure
Selective Removal of Semiconductor Fins
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Hybrid-Channel Nano-Sheet Fets
Selective Gas Etching for Self-Aligned Pattern Transfer
Nanosheet Field Effect Transistors with Partial Inside Spacers
Forming a Sacrificial Liner for Dual Channel Devices
Forming a Sacrificial Liner for Dual Channel Devices
Semiconductor Device with Reduced via Resistance
Semiconductor Device with Reduced via Resistance
Chip Guard Ring Including a Through-Substrate Via
Application:
61/161,111 →
Punch Through Stopper in Bulk Finfet Device
Application:
61/980,292 →
Finfet Device with Vertical Silicide on Recessed Source and Drain Epitaxy Regions
Application:
61/982,616 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 8, 2016
From: ADUSUMILLI, PRANEET; REZNICEK, ALEXANDER; VAN DER STRATEN, OSCAR; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040247/0437 →
Assignment of Assignor's Interest
Dec 7, 2016
From: BERGENDAHL, MARC A.; CHENG, KANGGUO; LIE, FEE LI; MILLER, ERIC A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040586/0318 →
Corrective Assignment to Correct the Conveying Party Data Previously Recorded on Reel 040586 Frame 0318. Assignor(S) Hereby Confirms the Assignment.
Dec 15, 2016
From: BERGENDAHL, MARC A.; CHENG, KANGGUO; LIE, FEE LI; MILLER, ERIC R.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040940/0578 →
Assignment of Assignor's Interest
Mar 6, 2017
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; KHAKIFIROOZ, ALI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041477/0006 →
Assignment of Assignor's Interest
May 31, 2017
From: BRIGGS, BENJAMIN D.; NOGAMI, TAKESHI; PATLOLLA, RAGHUVEER R.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 042547/0245 →
Assignment of Assignor's Interest
Jun 21, 2017
From: BU, HUIMING; CHENG, KANGGUO; GUO, DECHAO; KANAKASABAPATHY, SIVANANDA K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 042772/0143 →
Assignment of Assignor's Interest
Oct 30, 2017
From: GUILLORN, MICHAEL A.; HOOK, TERRENCE B.; ROBISON, ROBERT R.; VEGA, REINALDO A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 043983/0765 →
Assignment of Assignor's Interest
Dec 14, 2017
From: LIE, FEE LI; SHAO, DONGBING; WONG, ROBERT; XU, YONGAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044889/0473 →
Assignment of Assignor's Interest
Dec 21, 2017
From: AOKI, TOYOHIRO; HISADA, TAKASHI; HORIBE, AKIHIRO; HADA, SAYURI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044462/0933 →
Assignment of Assignor's Interest
Dec 29, 2017
From: BRIGGS, BENJAMIN DAVID; LEE, JOE; STANDAERT, THEODORUS EDUARDUS
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044985/0142 →
Assignment of Assignor's Interest
Dec 29, 2017
From: BRIGGS, BENJAMIN DAVID; LEE, JOE; STANDAERT, THEODORUS EDUARDUS
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044985/0152 →
Assignment of Assignor's Interest
Feb 15, 2018
From: MURRAY, CONAL E.; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044943/0324 →
Assignment of Assignor's Interest
Jun 6, 2018
From: ADUSUMILLI, PRANEET; REZNICEK, ALEXANDER; VAN DER STRATEN, OSCAR; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 045998/0887 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Corrective Assignment to Correct the 16/161,111 Previously Recorded on Reel 051489 Frame 0324. Assignor(S) Hereby Confirms the Assignment.
Aug 3, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 053389/0252 →
Change of Name
Mar 24, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 059498/0010 →
Change of Name
Apr 29, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 059835/0051 →
Certificate of Conversion & Change of Name
Jun 15, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 060449/0357 →
Certificate of Conversion & Change of Name
Jun 27, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 060443/0792 →
Certificate of Conversion & Change of Name
Sep 7, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 061388/0199 →
Change of Name
Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0410 →
Change of Name
Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0454 →
Change of Name
Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0448 →
Change of Name
Nov 21, 2025
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 073658/0823 →
Change of Name
Nov 21, 2025
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 073658/0439 →