Bulk nanosheet with dielectric isolation
Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.
1. A method of forming a device structure with dielectric isolation, the method comprising:
forming a plurality of nanosheets of alternating material layers as a stack on a bulk semiconductor wafer, a bottom nanosheet material layer of the stack comprising Si and Ge;
etching through the plurality of nanosheets to form (i) two or more nanowire stacks on the bulk semiconductor wafer and (ii) one or more trenches between the two or more nanowire stacks such that a bottom surface of each of the one or more trenches is substantially coplanar with an interface between (i) the bulk semiconductor wafer and (ii) a bottom nanowire comprising Si and Ge;
subsequent to etching through the plurality of nanosheets, forming spacers covering sidewalls of the two or more nanowire stacks; and
oxidizing a top portion of the bulk semiconductor wafer through each of the one or more trenches, wherein the oxidizing forms a dielectric isolation region in the top portion of the bulk semiconductor wafer.
2. The method of claim 1 , further comprising:
prior to forming the plurality of nanosheets as the stack on the bulk semiconductor wafer, forming a dopant implantation region in the top portion of the bulk semiconductor wafer.
3. The method of claim 2 , wherein forming a dopant implantation region in the top portion of the bulk semiconductor wafer comprises implanting a dopant into the top portion of the bulk semiconductor wafer at a dose of from approximately 5×10 15 atoms/cm 2 to about 5×10 16 atoms/cm 2 .
4. The method of claim 1 , wherein the top portion of the bulk semiconductor wafer comprises a first thickness of from about 100 angstroms to about 500 angstroms of the bulk semiconductor wafer.
5. The method of claim 1 , wherein the plurality of nanosheets comprises alternating layers of a sacrificial material and a channel material as the stack on the bulk semiconductor wafer.
6. The method of claim 5 , wherein the sacrificial material comprises silicon germanium (SiGe) and the channel material comprises silicon (Si).
7. The method of claim 1 , wherein the bottom nanosheet material layer in the stack adjacent to the bulk semiconductor wafer is thicker than other nanosheets in the stack.
8. The method of claim 7 , wherein the bottom nanosheet material layer has a thickness of from about 20 nanometers to about 35 nanometers.
9. The method of claim 7 , wherein individual nanosheets in the stack other than the bottom nanosheet material layer have a thickness of from about 10 nanometers to about 25 nanometers.
10. The method of claim 5 , wherein the sacrificial material comprises silicon germanium (SiGe) and the channel material comprises Si, and wherein the oxidizing results in an inverted triangular-shaped region of the Si and Ge in the bottom nanowires of the two or more nanowire stacks.
11. The method of claim 1 , further comprising:
filling each of the one or more trenches with a trench oxide prior to oxidizing the top portion of the bulk semiconductor wafer.
12. The method of claim 11 , wherein the trench oxide fully fills each of the one or more trenches in between the spacers.
13. The method of claim 11 , wherein the trench oxide comprises silicon dioxide (SiO 2 ) deposited using a high density plasma (HDP) or chemical vapor deposition (CVD) process.
14. The method of claim 1 , wherein the oxidizing comprises:
annealing the bulk semiconductor wafer in an oxygen ambient under conditions sufficient to form the dielectric isolation region in the top portion of the bulk semiconductor wafer.
15. The method of claim 1 , wherein the dielectric isolation region is continuous along the top portion of the bulk semiconductor wafer beneath the nanowire stacks.
16. The method of claim 1 , wherein the spacers are formed from a nitride material.
17. The method of claim 2 , wherein forming a dopant implantation region comprises implanting phosphorous in the top portion of the bulk semiconductor wafer.
18. The method of claim 2 , wherein forming a dopant implantation region comprises implanting fluorine in the top portion of the bulk semiconductor wafer.
19. A method of forming a device structure with dielectric isolation, the method comprising:
doping a top portion of a bulk semiconductor wafer;
subsequently forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form two or more nanowire stacks and one or more trenches between the two or more nanowire stacks until a planar surface of the top portion of the bulk semiconductor wafer is exposed;
forming spacers covering sidewalls of the two or more nanowire stacks; and
oxidizing the top portion of the bulk semiconductor wafer through the one or more trenches, wherein the oxidizing forms a dielectric isolation region in the top portion of the bulk semiconductor wafer.