Patent Assignment
Reel/Frame 069067/0454
Change of Name
Recorded: 2024-09-27
Pages: 7
Assignor
TESSERA LLC
Executed: 2022-08-15
Assignee
ADEIA SEMICONDUCTOR SOLUTIONS LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(99)
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Self-Forming Embedded Diffusion Barriers
Selective Removal of Semiconductor Fins
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Silicon Nitride Fill for Pc Gap Regions to Increase Cell Density
Iii-V Compound and Germanium Compound Nanowire Suspension with Germanium-Containing Release Layer
Patent:
9,390,980 →
Application:
14/666,520 →
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Self-Forming Embedded Diffusion Barriers
Bulk Nanosheet with Dielectric Isolation
Self Aligned Replacement Metal Source/Drain Finfet
Patent:
9,466,693 →
Application:
14/943,652 →
Stable Work Function for Narrow-Pitch Devices
Patent:
9,583,486 →
Application:
14/946,245 →
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Gate Stack with Tunable Work Function
Patent:
9,583,400 →
Application:
14/996,563 →
Methods of Fabricating Semiconductor Fins by Double Sidewall Image Transfer Patterning Through Localized Oxidation Enhancement of Sacrificial Mandrel Sidewalls
Self Aligned Replacement Metal Source/Drain Finfet
Air Gap Spacer for Metal Gates
Patent:
9,608,065 →
Application:
15/173,132 →
Iii-V Compound and Germanium Compound Nanowire Suspension with Germanium-Containing Release Layer
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Self-Forming Barrier for Use in Air Gap Formation
Gate Cut with Integrated Etch Stop Layer
Fabrication of Nano-Sheet Transistors with Different Threshold Voltages
Patent:
9,653,289 →
Application:
15/268,993 →
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Stable Work Function for Narrow-Pitch Devices
Stacked Transistors with Different Channel Widths
Patent:
9,660,028 →
Application:
15/339,665 →
Air Gap Spacer for Metal Gates
Hybrid-Channel Nano-Sheet Fets
Patent:
9,972,542 →
Application:
15/398,232 →
Memristive Device Based on Alkali-Doping of Transitional Metal Oxides
Selective Removal of Semiconductor Fins
Fabrication of Nano-Sheet Transistors with Different Threshold Voltages
Nano-Sheet Transistors with Different Threshold Voltages
Stacked Transistors with Different Channel Widths
Sacrificial Mandrel Structure with Oxide Pillars having Different Widths and Resulting Fins Arrangements
Two Dimension Material Fin Sidewall
Patent:
9,947,660 →
Application:
15/489,920 →
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Bulk Nanosheet with Dielectric Isolation
Sidewall Image Transfer (SIT) Methods with Localized Oxidation Enhancement of Sacrificial Mandrel Sidewall by Ion Beam Exposure
Bulk Nanosheet with Dielectric Isolation
Air Gap Spacer for Metal Gates
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Hybrid-Channel Nano-Sheet Fets
Two Dimension Material Fin Sidewall
Two Dimension Material Fin Sidewall
Silicon Nitride Fill for Pc Gap Regions to Increase Cell Density
Stable Work Function for Narrow-Pitch Devices
Finfet Gate Cut After Dummy Gate Removal
Patent:
10,229,854 →
Application:
15/841,933 →
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Two Dimension Material Fin Sidewall
Hybrid-Channel Nano-Sheet Fets
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Air Gap Spacer for Metal Gates
Method of Fabricating Semiconductor Fins by Enhancing Oxidation of Sacrificial Mandrels Sidewalls through Angled Ion Beam Exposure
Two Dimension Material Fin Sidewall
Two Dimension Material Fin Sidewall
Gate Cut with Integrated Etch Stop Layer
Gate Cut with Integrated Etch Stop Layer
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Stacked Transistors with Different Channel Widths
Finfet Gate Cut After Dummy Gate Removal
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Bulk Nanosheet with Dielectric Isolation
Self Aligned Replacement Metal Source/Drain Finfet
Selective Removal of Semiconductor Fins
Hybrid-Channel Nano-Sheet Fets
Gate Cut with Integrated Etch Stop Layer
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Two Dimension Material Fin Sidewall
Finfet Gate Cut After Dummy Gate Removal
Air Gap Spacer for Metal Gates
Stacked Transistors with Different Channel Widths
Self Aligned Replacement Metal Source/Drain Finfet
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Method of Fabricating Semiconductor Fins by Differentially Oxidizing Mandrel Sidewalls
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Gate Cut with Integrated Etch Stop Layer
Fabrication of Nano-Sheet Transistors with Different Threshold Voltages
Patent:
49,954 →
Application:
17/338,459 →
Hybrid-Channel Nano-Sheet Fets
Finfet Gate Cut After Dummy Gate Removal
Patent:
50,613 →
Application:
17/702,626 →
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Patent:
50,174 →
Application:
17/710,394 →
Self-Forming Embedded Diffusion Barriers
Patent:
50,494 →
Application:
17/710,403 →
Selective Removal of Semiconductor Fins
Application:
17/750,953 →
Publication:
US 2022/0344211
Two Dimension Material Fin Sidewall
Package-On-Package Assembly with Wire Bonds to Encapsulation Surface
Bulk Nanosheet with Dielectric Isolation
Stable Work Function for Narrow-Pitch Devices
Application:
17/900,205 →
Publication:
US 2023/0299170
Stacked Transistors with Different Channel Widths
Air Gap Spacer for Metal Gates
Gate Cut with Integrated Etch Stop Layer
Air Gap Spacer Formation for Nano-Scale Semiconductor Devices
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Gate Cut with Integrated Etch Stop Layer
Fabrication of Nano-Sheet Transistors with Different Threshold Voltages
Application:
18/618,766 →
Structure and Method to Improve Fav Rie Process Margin and Electromigration
Application:
18/677,474 →
Publication:
US 2025/0132199
Self Aligned Replacement Metal Source/Drain Finfet
Application:
18/768,635 →
Publication:
US 2025/0142872
Gate Cut with Integrated Etch Stop Layer
Application:
18/776,819 →
Publication:
US 2025/0142949
Structure and Process to Tuck Fin Tips Self-Aligned to Gates
Application:
18/794,367 →
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Assignment of Assignor's Interest
Jan 6, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051489/0557 →
Assignment of Assignor's Interest
Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name
Mar 24, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 059498/0010 →
Change of Name
Apr 29, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 059835/0051 →
Certificate of Conversion & Change of Name
Jun 27, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 060443/0792 →
Certificate of Conversion & Change of Name
Oct 7, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 061623/0936 →