Two dimension material fin sidewall
View Patent ↗A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
1. A semiconductor structure fabrication method comprising:
forming neighboring fins within a semiconductor substrate separated by a fin well;
forming a fin cap upon each fin;
forming a 2D material upon sidewalls fins and upon a bottom surface of the fin well within a source region, within a drain region, and within a channel region;
forming a channel mask upon the 2D material and upon the fin caps within the channel region;
forming a source contact adjacent to the channel mask within the source region and forming a drain contact adjacent to the channel mask within the drain region;
exposing the 2D material and the fin caps within the channel region by removing the channel mask;
forming a gate dielectric upon the exposed 2D material and upon the exposed fin caps within the channel region; and
forming a gate upon the gate dielectric.
2. The method of claim 1 , wherein the 2D material is formed as a layer upon sidewalls of each fin, not formed upon the fin caps, and formed upon the bottom surface of the fin well.
3. The method of claim 1 , wherein the semiconductor substrate and the fins are formed from Silicon Carbide.
4. The method of claim 1 , wherein the 2D material is Graphene.
5. The method of claim 1 , further comprising:
forming a source/drain contact mask upon the source contact, upon the drain contact, and upon the channel mask; and
simultaneously removing the channel mask and the source/drain contact mask thereupon.
6. The method of claim 5 , wherein simultaneously removing the channel mask and the source/drain contact mask thereupon comprises:
resultantly forming a channel well that exposes the 2D material and the fin caps within the channel region.
7. The method of claim 1 , wherein forming the forming neighboring fins and forming fin caps comprises:
forming a fin cap layer upon the semiconductor substrate;
forming a mandrel base layer upon the fin cap layer;
forming mandrels upon the mandrel base layer;
forming spacers upon sidewalls of the mandrels;
forming the mandrels within spacers;
forming a fin mask by removing the fin cap layer and the mandrel base layer while retaining the fin cap layer and the mandrel base layer underneath the spacers; and
forming fins and fin caps by removing the fin mask and partially removing exposed portions of substrate not protected by the fin mask while retaining a portion of the fin cap layer upon the upper surface of each formed fin.
8. The method of claim 1 , wherein the fin caps are formed from a material that which the 2D material does not form thereupon when the 2D material is formed upon sidewalls of the fin well and upon the bottom surface of the fin well.
9. A semiconductor structure comprising:
a substrate;
neighboring fins within the substrate separated by a fin well;
a fin cap upon each fin;
a 2D material upon sidewalls of the fins and upon a bottom surface of the fin well within a source region, within a drain region, and within a channel region;
a source contact within the source region and a drain contact within the drain region;
a gate dielectric upon the 2D material and upon the fin caps within the channel region; and
a gate upon the gate dielectric.
10. The semiconductor structure of claim 9 , wherein the 2D material is upon sidewalls of each fin, not upon the fin caps, and upon the bottom surface of the fin well.
11. The semiconductor structure of claim 9 , wherein the semiconductor substrate and the fins are formed from Silicon Carbide.
12. The semiconductor structure of claim 9 , wherein the 2D material is Graphene.
13. The semiconductor structure of claim 9 , wherein the gate dielectric is an Aluminum Oxide gate dielectric.
14. The semiconductor structure of claim 9 , wherein the fin caps are Silicon Nitride fin caps.
15. A finFET comprising:
a substrate;
neighboring fins within the substrate separated by a fin well;
a fin cap upon each fin;
a 2D material upon sidewalls of the fins and upon a bottom surface of the fin well within a source region, within a drain region, and within a channel region;
a source contact within the source region and a drain contact within the drain region;
a gate dielectric upon the 2D material and upon the fin caps within the channel region; and
a gate upon the gate dielectric.
16. The finFET of claim 15 , wherein the 2D material is upon sidewalls of each fin, not upon the fin caps, and upon the bottom surface of the fin well.
17. The finFET of claim 15 , wherein the semiconductor substrate is a Silicon Carbide semiconductor substrate and wherein the fins are Silicon Carbide fins.
18. The finFET of claim 15 , wherein the 2D material is Graphene.
19. The finFET of claim 15 , wherein the gate dielectric is an Aluminum Oxide gate dielectric.
20. The finFET of claim 15 , wherein the fin caps are Silicon Nitride fin caps.