Two dimension material fin sidewall
A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
1. A semiconductor structure fabrication method comprising:
forming a first fin and a second fin separated by a bottom well surface, each fin having a first sidewall, a second sidewall, and a top surface, wherein the second sidewall of the first fin, the first sidewall of the second fin, and the bottom well surface form a fin well;
forming a 2D material upon the fin well; and
forming a finFET device having a channel formed from the 2D material on the fin well, wherein the 2D material is not disposed upon the top surfaces of the first and second fins and the first and second fins each comprise a material that is a semiconductor.
2. The semiconductor structure fabrication method of claim 1 , wherein at least a portion of a source contact, a gate dielectric layer, a gate layer, and a drain contact are formed on the 2D material, and wherein the gate layer is formed on the gate dielectric layer.
3. The method of claim 1 , wherein the first and second fins comprise a silicon carbide material.
4. The method of claim 1 , wherein the 2D material is graphene.
5. The method of claim 1 , wherein forming the transistor device comprises depositing a high-k dielectric layer on the 2D material.
6. The method of claim 5 , wherein the high-k dielectric layer comprises an aluminum oxide.
7. The method of claim 1 , wherein the top surface of the first fin comprises a first fin cap and the top surface of the second fin comprises a second fin cap.
8. The method of claim 7 , wherein the first and second fin caps each comprise a silicon nitride.
9. The method of claim 7 , wherein the first and second fin caps each have a thickness of approximately 5 nm.
10. The method of claim 7 , wherein the first and second fin caps each have a thickness between 5 nm and 50 nm.
11. The method of claim 1 , wherein the 2D material has a thickness of approximately 0.35 nm.
12. The method of claim 1 , wherein the 2D material has a thickness of approximately 0.7 nm.
13. The method of claim 1 , wherein the 2D material has a thickness between 0.35 nm and 3.5 nm.
14. The method of claim 1 , wherein a depth of the fin well is substantially the same as a vertical height of the first fin.
15. The method of claim 1 , wherein the transistor device comprises a gate formed upon the 2D material, filling the fin well.
16. A semiconductor structure fabrication method comprising:
forming a first, second, and third fin, each fin having a first sidewall, a second sidewall, and a top surface, wherein:
the first, second, and third fin each comprise a material that is a semiconductor;
the first fin and the second fin are separated by a first bottom well surface;
the second fin and the third fin are separated by a second bottom well surface;
the second sidewall of the first fin, the first sidewall of the second fin, and the first bottom well surface form a first fin well; and
the second sidewall of the second fin, the first sidewall of the third fin, and the second bottom well surface form a second fin well;
forming a 2D material upon the first and second fin wells; and
forming a finFET device having a first discrete channel formed from the 2D material on the first fin well and a second discrete channel formed from the 2D material on the second fin well.
17. The method of claim 16 , wherein the 2D material is graphene.
18. The method of claim 16 , wherein the the first, second, and third fins comprise silicon carbide.
19. The method of claim 16 , wherein the transistor device comprises a high-k dielectric layer on top of the 2D material.
20. The method of claim 19 , wherein the high-k dielectric layer comprises an aluminum oxide.
21. The method of claim 16 , wherein the first sidewall and second sidewall are sloped relative to the first well.
22. The method of claim 16 , wherein the top surface of the first fin comprises a first fin cap, the top surface of the second fin comprises a second fin cap, and the top surface of the third fin comprises a third fin cap.
23. The method of claim 22 , wherein the first, second, and third fin caps each comprise a silicon nitride.
24. The method of claim 16 , wherein the 2D material has a thickness of approximately 0.35 nm.
25. The method of claim 16 , wherein the 2D material has a thickness between 0.35 nm and 3.5 nm.
26. The method of claim 16 , wherein a depth of the first fin well is substantially the same as a vertical height of the first fin.
27. The method of claim 16 , wherein the transistor device comprises a gate formed upon the 2D material, filling the first and second fin wells.