Two dimension material fin sidewall
View Patent ↗A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
1. A semiconductor structure fabrication method comprising:
forming neighboring fins associated with a semiconductor substrate, the neighboring fins separated by a fin well;
forming a fin cap upon each neighboring fin;
forming a well-plug within a bottom portion of the fin well such that sidewall portions of the neighboring fins are exposed to an upper portion of the fin well; and
forming a 2D material upon the sidewall portions of the neighboring fins.
2. The method of claim 1 , wherein the 2D material is formed upon the sidewall portions the neighboring fins and not formed upon the fin caps and not formed upon the majority of an upper surface of the well-plug.
3. The method of claim 1 , wherein the semiconductor substrate is a Silicon Carbide semiconductor substrate and wherein the neighboring fins are Silicon Carbide neighboring fins.
4. The method of claim 1 , wherein the 2D material is Graphene.
5. The method of claim 1 , wherein forming the well-plug comprises:
forming a blanket dielectric layer upon the substrate and upon the neighboring fins, and upon the fin caps; and
recessing the blanket dielectric layer by a chemical mechanical polish stopping at a plane coplanar with the fin caps top surface.
6. The method of claim 5 , wherein forming the well-plug further comprises:
subsequent to the recessing the blanket dielectric layer by a chemical mechanical polish stopping at a plane coplanar with the fin caps top surface, recessing the blanket layer by etching away the blanket layer within the upper portion of the fin well.
7. The method of claim 5 , wherein the well-plug is a silicon dioxide well-plug.
8. A semiconductor structure comprising:
a substrate;
neighboring fins associated with the substrate, the neighboring fins separated by a fin well;
a fin cap upon each neighboring fin;
a well-plug within a bottom portion of the fin well, wherein sidewall portions of the neighboring fins are exposed to an upper portion of the fin well;
a 2D material upon the exposed sidewall portions of the neighboring fins.
9. The semiconductor structure of claim 8 , wherein the 2D material is upon the sidewall portions of the neighboring fins and not upon the fin caps and not upon a majority of an upper surface of the well-plug.
10. The semiconductor structure of claim 8 , wherein the semiconductor substrate is a Silicon Carbide semiconductor substrate and wherein the neighboring fins are Silicon Carbide neighboring fins.
11. The semiconductor structure of claim 8 , wherein the 2D material is Graphene.
12. The semiconductor structure of claim 8 , wherein the well-plug is a silicon dioxide well-plug.
13. A finFET comprising:
a substrate;
neighboring fins associated with the substrate, the neighboring fins separated by a fin well;
a fin cap upon each neighboring fin;
a well-plug within a bottom portion of the fin well, wherein sidewall portions of the neighboring fins are exposed to an upper portion of the fin well; and
a 2D material upon the exposed sidewall portions of the neighboring fins.
14. The finFET of claim 13 , wherein the 2D material is upon the sidewall portions of each neighboring fin and not upon the fin caps and not upon a majority of an upper surface of the well-plug.
15. The finFET of claim 13 , wherein the semiconductor substrate is a Silicon Carbide semiconductor substrate and wherein the neighboring fins are Silicon Carbide neighboring fins.
16. The finFET of claim 13 , wherein the 2D material is Graphene.
17. The finFET of claim 13 , wherein the well-plug is a silicon dioxide well-plug.