Structure and method to improve FAV RIE process margin and electromigration
A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
1 . A semiconductor device, comprising:
a lower interconnect level comprising a first interlevel dielectric, ILD, and a plurality of parallel lower metal lines in an upper portion of the first ILD;
an upper interconnect level comprising a second ILD and an upper metal line in an upper portion of the second ILD;
a self-aligned via connecting the upper metal line to a first lower metal line, wherein:
the first ILD comprises a first ILD region disposed between the first lower metal line and an adjacent second lower metal line;
the second ILD comprises a second ILD region disposed on the first ILD region;
the first ILD region comprises a first material and the second ILD region comprises a second material different than the first material;
the first material is disposed adjacent to an interface between the first ILD region and the second ILD region and the second material is disposed adjacent to the same interface;
the second ILD region comprises opposing vertically-oriented sidewalls self-aligned to opposing vertically-oriented sidewalls of the first ILD region therebelow and separated by a distance less than a distance separating opposing vertically-oriented sidewalls of the first ILD region; and
the self-aligned via contacts the second ILD region.
2 . The semiconductor device of claim 1 , wherein the self-aligned via is wider at its interface with the upper metal line than at its interface with the first lower metal line.
3 . The semiconductor device of claim 1 , wherein a vertically-oriented sidewall of an upper portion of the self-aligned via is disposed over the second ILD region.
4 . The semiconductor device of claim 1 , wherein:
a lower portion of the self-aligned via is disposed between opposing portions of a liner, and
one of the opposing portions of the liner is disposed on one of the vertically-oriented sidewalls of the second ILD region.
5 . The semiconductor device of claim 4 , wherein the lower portion of the self-aligned via fully contacts an entire width of the lower metal line.
6 . The semiconductor device of claim 1 , wherein the self-aligned via contacts one of the vertically-oriented sidewalls of the second ILD region.
7 . The semiconductor device of claim 1 , wherein an upper surface of the first ILD region is substantially co-planar with an upper surface of the first lower metal line.
8 . The semiconductor device of claim 1 , wherein the distance between the vertically-oriented sidewalls of the second ILD region is defined directly above the interface.
9 . The semiconductor device of claim 1 , wherein the distance between the vertically-oriented sidewalls of the first ILD region is defined directly below the interface.
10 . The semiconductor device of claim 1 , wherein:
the distance between the vertically-oriented sidewalls of the second ILD region is defined directly above the interface; and
the distance between the vertically-oriented sidewalls of the first ILD region is defined directly below the interface.
11 . The semiconductor device of claim 1 , wherein a liner is disposed on portions of the vertically-oriented sidewalls of the second ILD region.
12 . The semiconductor device of claim 11 , wherein a lower portion of the self-aligned via fully contacts an entire width of the lower metal line.
13 . The semiconductor device of claim 11 , wherein:
a lower portion of the self-aligned via is disposed between opposing portions of the liner; and
one of the opposing portions of the liner is disposed on one of the vertically-oriented sidewalls of the second ILD region.
14 . The semiconductor device of claim 13 , wherein the lower portion of the self-aligned via fully contacts an entire width of the lower metal line.
15 . The semiconductor device of claim 11 , wherein the liner comprises nitride.
16 . The semiconductor device of claim 1 , wherein the self-aligned via contacts a substantially horizontal portion of the second ILD region.
17 . The semiconductor device of claim 16 , wherein:
the second ILD region is disposed on a first side of the self-aligned via; and
the self-aligned via further contacts a substantially horizontal portion of another second ILD region disposed on a second side of the self-aligned via opposite to the first side.
18 . The semiconductor device of claim 1 , wherein the plurality of parallel lower metal lines comprise Cu.
19 . The semiconductor device of claim 1 , wherein the self-aligned via comprises Cu.
20 . The semiconductor device of claim 1 , wherein the upper metal line comprises Cu.