Gate stack with tunable work function
View Patent ↗A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
1. A method for fabricating a gate stack of a semiconductor device, the method comprising:
forming a first dielectric layer over a channel region of the device;
forming a barrier layer over the first dielectric layer;
forming a first gate metal layer over the barrier layer;
forming a capping layer over the first gate metal layer;
removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack;
depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer;
depositing a scavenging layer on the first nitride layer;
depositing a second nitride layer on the scavenging layer; and
depositing a gate electrode material on the second nitride layer.
2. The method of claim 1 , wherein the first dielectric layer includes an oxide material.
3. The method of claim 1 , wherein the barrier layer includes a metal nitride material.
4. The method of claim 1 , wherein the first gate metal layer includes TiAlC or TiAl, Ti, Al, TiAlC, NbAlC.
5. The method of claim 1 , wherein the first nitride layer includes TiN or TaN.
6. The method of claim 1 , wherein the first nitride layer includes TaN.
7. The method of claim 1 , wherein the second nitride layer includes TiN.
8. The method of claim 1 , wherein the gate electrode material includes W.
9. The method of claim 1 , further comprising forming a source/drain region adjacent to the gate stack prior to forming the gate stack.
10. The method of claim 1 , further comprising prior to forming the gate stack:
forming a sacrificial gate stack over the channel region of the device;
forming a spacer along sidewalls of the sacrificial gate stack;
forming a source/drain region of the device adjacent to the sacrificial gate stack;
forming a layer of insulator material around the spacer; and
removing the sacrificial gate stack to expose the channel region of the device.
11. A semiconductor device comprising:
a gate stack arranged over a channel region of the device, the gate stack comprising an n-type field effect transistor (nFET) portion comprising:
a dielectric layer arranged on a substrate;
a barrier layer arranged on the dielectric layer;
a first gate metal layer arranged on the barrier layer;
a capping layer arranged on the first gate metal layer;
a first nitride layer arranged on the capping layer;
a scavenging layer arranged on the first nitride layer;
a second nitride layer arranged on the scavenging layer; and
a gate electrode arranged on the second nitride layer.
12. The device of claim 11 , further comprising a p-type field effect transistor (pFET) portion comprising:
the dielectric layer arranged on the substrate;
the first nitride layer arranged on the dielectric layer;
the scavenging layer arranged on the first nitride layer;
the second nitride layer arranged on the scavenging layer; and
the gate electrode arranged on the second nitride layer.
13. The device of claim 11 , wherein the first dielectric layer includes an oxide material.
14. The device of claim 11 , wherein the barrier layer includes a metal nitride material.
15. The device of claim 11 , wherein the gate electrode material includes W.
16. A semiconductor device comprising:
a gate stack arranged over a channel region of the device, the gate stack comprising:
an n-type field effect transistor (nFET) portion comprising:
a dielectric layer arranged on a substrate;
a barrier layer arranged on the dielectric layer;
a first gate metal layer arranged on the barrier layer;
a capping layer arranged on the first gate metal layer;
a first nitride layer arranged on the capping layer;
a scavenging layer arranged on the first nitride layer;
a second nitride layer arranged on the scavenging layer; and
a gate electrode arranged on the second nitride layer; and
a p-type field effect transistor (pFET) portion comprising:
the dielectric layer arranged on the substrate;
the first nitride layer arranged on the dielectric layer;
the scavenging layer arranged on the first nitride layer;
the second nitride layer arranged on the scavenging layer; and
the gate electrode arranged on the second nitride layer.
17. The device of claim 16 , wherein the first dielectric layer includes an oxide material.
18. The device of claim 16 , wherein the barrier layer includes a metal nitride material.
19. The device of claim 16 , wherein the gate electrode material includes W.