Stable work function for narrow-pitch devices
View Patent ↗A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
1. A field effect transistor structure, comprising:
a plurality of fins structures;
a gate structure disposed over and between the fin structures, the gate structure including:
a gate dielectric layer;
a diffusion prevention layer formed on the gate dielectric;
a continuous aluminum doped TiC layer having a thickness greater than 5 nm formed on the diffusion prevention layer and formed by pinching off portions of the aluminum doped TiC layer within the diffusion prevention layer to merge the portions without intervening layers between the portions; and
source and drain regions formed on sides of the gate structure on the plurality of fin structures.
2. The structure as recited in claim 1 , wherein the fin structures include semiconductor fins.
3. The structure as recited in claim 1 , wherein the fin structures include two or more stacked nanosheets.
4. The structure as recited in claim 3 , wherein the two or more stacked nanosheets each includes a semiconductor layer and the semiconductor layers are separated by a work function setting metal stack including:
a high dielectric constant layer;
a diffusion prevention layer formed on the high dielectric constant layer; and
an aluminum doped TiC layer having a thickness greater than 5 nm.
5. The structure as recited in claim 4 , further comprising an interface layer formed on the semiconductor layer.
6. The structure as recited in claim 1 , wherein the diffusion prevention layer includes a TiN layer.
7. The structure as recited in claim 1 , wherein the aluminum doped TiC layer includes an aluminum concentration of between about 20% and about 40%.
8. A field effect transistor structure, comprising:
a plurality of fins structures;
a gate structure disposed over and between the fin structures, the gate structure including:
a gate dielectric layer;
a diffusion prevention layer formed on the gate dielectric;
a continuous aluminum doped center layer formed on the diffusion prevention layer and formed by pinching off portions of the aluminum doped center layer within the diffusion prevention layer to merge the portions without intervening layers between the portions; and
source and drain regions formed on sides of the gate structure on the plurality of fin structures.
9. The structure as recited in claim 8 , wherein the fin structures include semiconductor fins.
10. The structure as recited in claim 8 , wherein the fin structures include two or more stacked nanosheets.
11. The structure as recited in claim 10 , wherein the two or more stacked nano sheets each includes a semiconductor layer and the semiconductor layers are separated by a work function setting metal stack including:
a high dielectric constant layer;
a diffusion prevention layer formed on the high dielectric constant layer; and
an aluminum doped TiC layer having a thickness greater than 5 nm.
12. The structure as recited in claim 11 , further comprising an interface layer formed on the semiconductor layer.
13. The structure as recited in claim 8 , wherein the diffusion prevention layer includes a TiN layer.
14. The structure as recited in claim 8 , wherein the continuous aluminum doped center layer includes an aluminum doped TiC layer.
15. The structure as recited in claim 14 , wherein the aluminum doped TiC layer includes an aluminum concentration of between about 20% and about 40%.