Selective removal of semiconductor fins
An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.
1. A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor fins on a substrate;
forming a material liner on physically exposed surfaces of said plurality of semiconductor fins and said substrate;
applying and patterning a photoresist layer over said material liner, wherein at least a semiconductor fin is positioned between a pair of sidewalls of said patterned photoresist layer;
implanting an implant material into a top portion of said material liner employing an angled implantation process, wherein a first sidewall portion of said material liner located on one side of said semiconductor fin and a top portion of said material liner are converted into an compound material portion, and said implant material is not implanted into a second sidewall portion of said material liner located on another side of semiconductor fin;
removing said compound material portion selective to remaining portions of said material liner that are not implanted with said implant material; and
removing at least a portion of said semiconductor fin selective to said remaining portions of said material liner.
2. The method of claim 1 , wherein said material liner comprises a dielectric material, a semiconductor material or a conductive material.
3. The method of claim 1 , further comprising:
forming a cavity by recessing said semiconductor fin selective to said remaining portions of said material liner; and
forming a dielectric material portion in said cavity by depositing a dielectric material in said cavity.
4. The method of claim 3 , further comprising forming a shallow trench isolation layer on a portion of said material liner, wherein a topmost surface of said dielectric material portion is coplanar with a top surface of said shallow trench isolation layer.
5. The method of claim 3 , wherein said recessing said semiconductor fin completely removes said semiconductor fin and a portion of said substrate underlying said semiconductor fin, wherein a bottommost surface of said cavity is located beneath a topmost surface of said substrate.
6. The method of claim 5 , wherein a bottom portion of said dielectric material portion is surrounded by said substrate.
7. The method of claim 3 , wherein said recessing said semiconductor fin removes a portion of said semiconductor fin to provide a semiconductor material portion, wherein said dielectric material portion is located atop said semiconductor material portion and has a width the same as a width of said semiconductor material portion.
8. The method of claim 3 , wherein said forming said plurality of semiconductor fins comprises:
providing a bulk semiconductor substrate; and
patterning a top portion of said bulk semiconductor substrate into said plurality of semiconductor fins, wherein an unpatterned bottom portion of said bulk semiconductor substrate constitutes said substrate, and said cavity is formed within said unpatterned bottom portion of said bulk semiconductor substrate.
9. The method of claim 1 , further comprising etching at least a region of said remaining portion of said material liner selective to said plurality of semiconductor fins.
10. The method of claim 1 , wherein said forming said plurality of semiconductor fins comprises:
providing a semiconductor-on-insulator substrate comprising a vertical stack of a handle substrate, a buried insulator layer and a top semiconductor layer; and
patterning the top semiconductor layer.
11. The method of claim 1 , wherein said implant material comprises Rn, Xe, Kr, Ar or Ne.
12. The method of claim 1 , wherein said implant material comprises Ge or Si.
13. The method of claim 1 , wherein an angle of said angled implantation process is from 5 degrees to 45 degrees.