Air gap spacer formation for nano-scale semiconductor devices
Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.
1. A method, comprising:
forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each, other with insulating material disposed between the first and second metallic structures;
etching the insulating material to form a space between the first and second metallic structures; and
depositing a layer of dielectric material over the first and second metallic structures to fort an air gap in the space between the first and second metallic structures;
wherein the first metallic structure comprises a gate structure of a transistor and wherein the second metallic structure comprises a source/drain contact;
wherein an upper portion of the air gap is disposed above an upper surface of the first metallic structure and below an upper surface of the second metallic structure; and
wherein a bottom portion of the air gap is disposed below a bottom surface of the second metallic structure.
2. The method of claim 1 , further comprising:
forming a BEOL (back-end-of-line) interconnect structure comprising a first metal line and a second metal line formed in an ILD (interlevel dielectric) layer, wherein the first metal line and the second metal line are disposed adjacent to each other with insulating material of the ILD layer disposed between the first and second metal lines;
etching the insulating material of the ILD layer to form from a space between the first and second metal lines; and
depositing a layer of dielectric material over the first and second metal lines to form an air gap in the space between the first and second metal lines:
wherein an upper portion of the air gap is disposed above upper surfaces of the first and second metal lines.
3. The method of claim 1 , wherein depositing a layer of dielectric material over the first and second metallic structures comprises:
depositing a non-conformal layer of dielectric material to form a dielectric capping layer having a pinch-off region that is aligned to the space between the first and second metallic structures;
wherein the pinch-off region is formed in the dielectric capping layer above the upper surface of the at least one first metallic structure and second metallic structure.
4. The method of claim 3 , wherein depositing the non-conformal layer of dielectric material comprises setting deposition parameters of a plasma-enhanced chemical vapor deposition process to obtain a level of conformality of about 40% or less.
5. The method of claim 1 , wherein the dielectric material comprises a low-k dielectric material having a dielectric constant that is about 5.0 or less.
6. The method of claim 1 , wherein the dielectric material comprises at least one of SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, SiC, p-SiCNH, and SiN.
7. The method of claim 1 , further comprising forming a conformal liner layer within the space between the first and second metallic structures before depositing the dielectric material over the first and second metallic structures to form the air gap in the space between the first and second metallic structures.
8. The method of claim 1 , wherein the transistor comprises a FIN-type FET (field effect transistor).
9. The method of claim 2 , wherein depositing a layer of dielectric material over the first and second metal lines comprises:
depositing a non-conformal layer of dielectric material over the first and second metal lines to form a dielectric capping layer having a pinch-off region that is aligned to the space between the first and second metal lines;
wherein the pinch-off region is formed in the dielectric capping layer above the upper surfaces of the first and second metal lines.
10. The method of claim 9 , wherein depositing the non-conformal layer of dielectric material over the first and second metal lines comprises setting deposition parameters of a plasma-enhanced chemical vapor deposition process to obtain a level of conformality of about 40% or less.
11. The method of claim 2 , wherein the dielectric material deposited over the first and second metal lines comprises a low-k dielectric material having a dielectric constant that is about 5.0 or less.
12. The method of claim 2 , wherein the dielectric material deposited over the first and second metal lines comprises at least one of SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, SiC, p-SiCNH, and SiN.
13. The method of claim 2 , further comprising forming a conformal liner layer within the space between the first and second metal lines before depositing the dielectric material over the first and second metal lines to form the air gap in the space between the first and second metal lines.