Two dimension material fin sidewall
A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.
1. A semiconductor structure fabrication method comprising:
forming a first fin and a second fin within a semiconductor substrate, the first fin and the second fin separated by a fin well, the fin well comprising a first sidewall formed by the first fin, a second sidewall formed by the second fin, and a bottom surface formed by the semiconductor substrate;
forming a well-plug within a bottom portion of the fin well such that a portion of the first sidewall formed by the first fin is exposed and such that a portion of the second sidewall formed by the second fin is exposed;
forming a 2D material upon the exposed portion of the first sidewall and upon the exposed portion of the second sidewall.
2. The method of claim 1 , wherein the 2D material is not formed upon the majority of an upper surface of the well-plug.
3. The method of claim 1 , wherein the semiconductor substrate is a Silicon Carbide semiconductor substrate, wherein the first fin is a Silicon Carbide first fin, and wherein the second fin is a Silicon Carbide second fin.
4. The method of claim 1 , wherein the 2D material is Graphene.
5. The method of claim 1 , wherein forming the well-plug comprises:
forming a blanket dielectric layer upon the substrate and upon the fins; and
recessing the blanket dielectric layer by a chemical mechanical polish stopping at a plane coplanar with the upper surface of the first fin and with the upper surface of the second fin.
6. The method of claim 5 , wherein forming the well-plug comprises:
subsequently recessing the blanket layer by etching away the blanket layer within an upper portion of the fin well.
7. The method of claim 1 , wherein the first sidewall formed by the first fin is obtusely angled relative to the bottom surface formed by the semiconductor substrate.
8. The method of claim 1 , wherein the 2D material is further formed upon an upper surface of the first fin and upon an upper surface of the second fin.
9. A semiconductor structure comprising:
a semiconductor substrate;
a first fin and a second fin within the semiconductor substrate, the first fin and the second fin separated by a fin well, the fin well comprising a first sidewall formed by the first fin, a second sidewall formed by the second fin, and a bottom surface formed by the semiconductor substrate;
a well-plug within a bottom portion of the fin well such that a portion of the first sidewall formed by the first fin is exposed and such that a portion of the second sidewall formed by the second fin is exposed;
a 2D material upon the exposed portion of the first sidewall and upon the exposed portion of the second sidewall.
10. The semiconductor structure of claim 9 , wherein the 2D material is not formed upon the majority of an upper surface of the well-plug.
11. The semiconductor structure of claim 9 , wherein the semiconductor substrate is a Silicon Carbide semiconductor substrate, the first fin is a Silicon Carbide first fin, and the second fin is a Silicon Carbide second fin.
12. The semiconductor structure of claim 9 , wherein the 2D material is Graphene.
13. The semiconductor structure of claim 9 , wherein the 2D material is further upon an upper surface of the first fin and upon an upper surface of the second fin.
14. The semiconductor structure of claim 9 , wherein the well-plug is a Silicon Dioxide well-plug.
15. A finFET comprising:
a semiconductor substrate;
a first fin and a second fin within the semiconductor substrate, the first fin and the second fin separated by a fin well, the fin well comprising a first sidewall formed by the first fin, a second sidewall formed by the second fin, and a bottom surface formed by the semiconductor substrate;
a well-plug within a bottom portion of the fin well such that a portion of the first sidewall formed by the first fin is exposed and such that a portion of the second sidewall formed by the second fin is exposed;
a 2D material upon the exposed portion of the first sidewall and upon the exposed portion of the second sidewall.
16. The finFET of claim 15 , wherein the 2D material is not formed upon the majority of an upper surface of the well-plug.
17. The finFET of claim 15 , wherein the semiconductor substrate is a Silicon Carbide semiconductor substrate, the first fin is a Silicon Carbide first fin, and the second fin is a Silicon Carbide second fin.
18. The finFET of claim 15 , wherein the 2D material is Graphene.
19. The finFET of claim 15 , wherein the 2D material is further upon an upper surface of the first fin and upon an upper surface of the second fin.
20. The finFET of claim 15 , wherein the well-plug is a Silicon Dioxide well-plug.