FinFET gate cut after dummy gate removal
Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.
1. A semiconductor integrated circuit, comprising:
a first semiconductor fin;
a first gate stack formed over the first semiconductor fin; and
a first gate cut plug fin at an end of the first gate stack, comprising a first layer of dielectric material and a second layer of planarizing material, the first layer of dielectric material located at least in part under the second layer of planarizing material and between the second layer of planarizing material and the first gate stack.
2. The semiconductor integrated circuit of claim 1 , wherein the first gate cut plug fin has a vertical profile.
3. The semiconductor integrated circuit of claim 1 , further comprising a second semiconductor fin parallel to the first semiconductor fin.
4. The semiconductor integrated circuit of claim 3 , further comprising a second gate stack formed over the second semiconductor fin and in line with the first gate stack.
5. The semiconductor integrated circuit of claim 4 , wherein the first gate cut plug fin is between and in line with the first gate stack and the second gate stack.
6. The semiconductor integrated circuit of claim 5 , further comprising third and fourth gate stacks, and a second gate cut plug fin,
wherein the third gate stack is parallel to the first gate stack, and
wherein the fourth gate stack is parallel to the second gate stack, and
wherein the second gate cut plug fin is between and in line with the third and fourth gate stacks.
7. The semiconductor integrated circuit of claim 1 , further comprising a plurality of spacer sidewalls, wherein the first layer of dielectric material is conformal on the spacer sidewalls and does not fill a space between the spacer sidewalls.
8. The semiconductor integrated circuit of claim 7 , wherein the second layer of planarizing material fills any space between the spacer sidewalls that is not filled by the first layer of dielectric material.
9. The semiconductor integrated circuit of claim 8 , wherein the first layer of dielectric material comprises a nitride-based dielectric and wherein the second layer of planarizing material comprises silicon dioxide.
10. The semiconductor integrated circuit of claim 9 , wherein the first layer of dielectric material comprises silicon nitride.
11. A semiconductor integrated circuit, comprising:
a first semiconductor fin;
a second semiconductor fin, the second semiconductor fin being parallel to the first semiconductor fin;
a first gate stack formed over the first semiconductor fin; and
a second gate stack formed over the second semiconductor fin; and
a first gate cut plug fin comprising:
a plurality of spacer sidewalls,
a first layer of dielectric material on the spacer sidewalls, and
a second layer of planarizing material that fills any space between the spacer sidewalls that is not filled by the first layer of dielectric material and that is surrounded and underlaid by the first layer of dielectric material,
wherein the first gate cut plug fin is between and in line with the first gate stack and the second gate stack.
12. The semiconductor integrated circuit of claim 11 , wherein the first gate cut plug fin has a vertical profile.
13. The semiconductor integrated circuit of claim 11 , further comprising third and fourth gate stacks, and a second gate cut plug fin,
wherein the third gate stack is parallel to the first gate stack, and
wherein the fourth gate stack is parallel to the second gate stack, and
wherein the second gate cut plug fin is between and in line with the third and fourth gate stacks.
14. The semiconductor integrated circuit of claim 11 , wherein the first layer of dielectric material comprises a nitride-based dielectric and wherein the second layer of planarizing material comprises silicon dioxide.
15. A semiconductor integrated circuit, comprising:
a first semiconductor fin;
a second semiconductor fin, the second semiconductor fin being parallel to the first semiconductor fin;
a first gate stack formed over the first semiconductor fin; and
a second gate stack formed over the second semiconductor fin; and
a first gate cut plug fin comprising a first layer of dielectric material and a second layer of planarizing material, the second layer of planarizing material over at least a portion of the first layer of dielectric material,
wherein the first gate cut plug fin is between and in line with the first gate stack and the second gate stack and the first layer of dielectric material separates the second layer of planarizing material from the first and second gate stacks.
16. The semiconductor integrated circuit of claim 15 , further comprising third and fourth gate stacks, and a second gate cut plug fin,
wherein the third gate stack is parallel to the first gate stack, and
wherein the fourth gate stack is parallel to the second gate stack, and
wherein the second gate cut plug fin is between and in line with the third and fourth gate stacks.
17. The semiconductor integrated circuit of claim 15 , further comprising a plurality of spacer sidewalls, wherein the first layer of dielectric material is conformal on the spacer sidewalls and does not fill a space between the spacer sidewalls.
18. The semiconductor integrated circuit of claim 17 , wherein the second layer of planarizing material fills any space between the spacer sidewalls that is not filled by the first layer of dielectric material.
19. The semiconductor integrated circuit of claim 15 , wherein the first layer of dielectric material comprises a nitride-based dielectric and wherein the second layer of planarizing material comprises silicon dioxide.
20. The semiconductor integrated circuit of claim 19 , wherein the first layer of dielectric material comprises silicon nitride.