Stacked transistors with different channel widths
A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.
1. A semiconductor integrated circuit comprising:
a first stack of nanowires above a semiconductor substrate;
a first gate structure over, around, and between the first stack of nanowires;
a second stack of nanowires above the semiconductor substrate;
a second gate structure over, around, and between the second stack of nanowires;
a first source/drain region contacting a first number of nanowires of the first nanowire stack; and
a second source/drain region contacting a second number of nanowires of the second nanowire stack, wherein:
the first number and the second number of contacted nanowires are different;
the first source/drain region is disposed directly on the semiconductor substrate; and
the second source/drain region is disposed on a dielectric region.
2. The semiconductor integrated circuit of claim 1 , wherein the first and second stacks of nanowires comprise a same number of nanowires.
3. The semiconductor integrated circuit of claim 1 , wherein the dielectric region comprises a low-k dielectric material.
4. The semiconductor integrated circuit of claim 1 , wherein the dielectric region comprises silicon oxide, silicon nitride, or silicon oxynitride.
5. The semiconductor integrated circuit of claim 1 , wherein the dielectric region comprises SiOCN or SiBCN.
6. The semiconductor integrated circuit of claim 1 , wherein a bottom surface of the dielectric region is substantially coplanar with a bottom surface of the first source/drain region.
7. The semiconductor integrated circuit of claim 1 , wherein nanowires of the second stack of nanowires disposed below the second source/drain region contact the dielectric region.
8. The semiconductor integrated circuit of claim 1 , wherein an uppermost nanowire of the first nanowire stack is substantially coplanar with an uppermost nanowire of the second nanowire stack.
9. The semiconductor integrated circuit of claim 1 , wherein a lowermost nanowire of the first nanowire stack is substantially coplanar with a lowermost nanowire of the second nanowire stack.
10. The semiconductor integrated circuit of claim 1 , further comprising an interlevel dielectric disposed on and around the first and second source/drain regions.
11. The semiconductor integrated circuit of claim 1 , further comprising:
a third stack of nanowires above the semiconductor substrate;
a third gate structure over, around, and between the third stack of nanowires; and
a third source/drain region contacting a third number of nanowires of the third nanowire stack, wherein:
the number of nanowires in the first, second, and third nanowire stacks is the same; and
the first, second, and third numbers of contacted nanowires are different.
12. A semiconductor integrated circuit comprising:
a first stack of nanowires above a substrate, each of the nanowires surrounded by a first gate structure;
a second stack of nanowires above the substrate, each of the nanowires surrounded by a second gate structure;
a first source/drain region contacting a first number of nanowires of the first nanowire stack; and
a second source/drain region contacting a second number of nanowires of the second nanowire stack, wherein:
the first number and the second number of contacted nanowires are different; and
the first and second stacks of nanowires comprise a same number of nanowires.
13. The semiconductor integrated circuit of claim 12 , wherein an uppermost nanowire of the first nanowire stack is substantially coplanar with an uppermost nanowire of the second nanowire stack.
14. The semiconductor integrated circuit of claim 12 , wherein a lowermost nanowire of the first nanowire stack is substantially coplanar with a lowermost nanowire of the second nanowire stack.
15. The semiconductor integrated circuit of claim 12 , further comprising:
a third stack of nanowires above the substrate, each of the nanowires surrounded by a third gate structure; and
a third source/drain region contacting a third number of nanowires of the third nanowire stack, wherein:
the number of nanowires in the first, second, and third nanowire stacks is the same; and
the first, second, and third numbers of contacted nanowires are different.
16. A semiconductor integrated circuit comprising:
a first stack of nanowires above a substrate;
a first gate structure over, around, and between the first stack of nanowires;
a second stack of nanowires above the substrate;
a second gate structure over, around, and between the second stack of nanowires;
a first source/drain region contacting a first number of nanowires of the first nanowire stack; and
a second source/drain region contacting a second number of nanowires of the second nanowire stack, wherein:
the first number and the second number of contacted nanowires are different; and
a vertical cross-section of the first gate structure between an uppermost nanowire of the first stack of nanowires and the substrate is substantially the same as a vertical cross-section of the second gate structure between an uppermost nanowire of the second stack of nanowires and the substrate.
17. The semiconductor integrated circuit of claim 16 , wherein an uppermost nanowire of the first nanowire stack is substantially coplanar with an uppermost nanowire of the second nanowire stack.
18. The semiconductor integrated circuit of claim 16 , wherein a lowermost nanowire of the first nanowire stack is substantially coplanar with a lowermost nanowire of the second nanowire stack.
19. The semiconductor integrated circuit of claim 16 , further comprising:
a third stack of nanowires above the substrate;
a third gate structure over, around, and between the third stack of nanowires; and
a third source/drain region contacting a third number of nanowires of the third nanowire stack, wherein:
the number of nanowires in the first, second, and third nanowire stacks is the same; and
the first, second, and third numbers of contacted nanowires are different.