Stacked transistors with different channel widths

1. A semiconductor device comprising:

a first stack of nanowires over a substrate;

a first dielectric layer over the substrate, the first dielectric layer having a first thickness;

a first source/drain region and a second source/drain region over the first dielectric layer;

a second stack of nanowires over the substrate;

a second dielectric layer over the substrate, the second dielectric layer having a second thickness, the second thickness differing from the first thickness; and

a third source/drain region and a fourth source/drain region over the second dielectric layer;

a third stack of nanowires directly on the substrate, so as to have no third dielectric layer present between the third stack of nanowires and the substrate; and

a fifth source/drain region and a sixth source/drain region directly on the substrate;

wherein a first height of the first and second source/drain regions, a second height of the third and fourth source/drain regions, and a third height of the fifth and sixth source/drain regions differ, the first height, the second height, and the third height differing in relation to a distance from the substrate.

2. The device of claim 1 , wherein:

the first source/drain region and the second source/drain region each has a third thickness;

the third source/drain region and the fourth source/drain region each has a fourth thickness; and

the fourth thickness differs from the third thickness.

3. The device of claim 2 , wherein:

a first number of nanowires in the first stack connect the first source/drain region to the second source/drain region;

a second number of nanowires in the second stack connect the third source/drain region to the fourth source/drain region; and

the second number differs from the first number.

4. The device of claim 3 , wherein a total number of nanowires in the first stack is equal to a total number of nanowires in the second stack.

5. The device of claim 4 , further comprising a gate structure on each of the nanowires in the first stack, on each of the nanowires in the second stack, and on each of the nanowires in the third stack, the gate structure including a gate dielectric material, a work function metal, and a gate conductor material.

6. The device of claim 5 , further comprising first spacers between the gate structure and each of the source/drain regions.

7. The device of claim 6 , further comprising an inter-level dielectric layer over the first dielectric layer, the first source/drain region, the second source/drain region, the second dielectric layer, the third source/drain region, and the fourth source/drain region.

8. The device of claim 7 , further comprising second spacers on the first spacers, the second spacers being between the inter-level dielectric layer and the gate structure.

9. The device of claim 8 , wherein the nanowires include a silicon material.

10. A semiconductor device comprising:

a first stack of nanowires over a substrate, wherein a first intervening layer is between first stack of nanowires and the substrate, the first intervening layer having a first thickness, wherein first source/drain regions having a first height are on top of the first intervening layer;

a second stack of nanowires over the substrate, wherein a second intervening layer is between the second stack of nanowires and the substrate, the second intervening layer having a second thickness, wherein second source/drain regions having a second height are on top of the second intervening layer, the second thickness differing from the first thickness;

a third stack of nanowires directly on top of the substrate such that no intervening third layer is present between the third stack of nanowires and the substrate, wherein third source/drain regions having a third height are directly on top of the substrate, each of the first, second, and third heights differing; and

a number of active nanowires in the first, second, and third stacks according to a difference in the first, second, and third heights.