Sacrificial mandrel structure with oxide pillars having different widths and resulting fins arrangements
View Patent ↗A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.
1. An intermediate fin field effect transistor (FinFET) structure, comprising:
a semiconductor substrate;
a nitride layer directly on the semiconductor substrate;
an oxide layer directly on the nitride layer;
a sacrificial mandrel directly on the oxide layer, wherein the oxide layer is between the sacrificial mandrel and the nitride layer, and wherein the sacrificial mandrel has a width in the range of about 20 nm to about 400 nm, and wherein the sacrificial mandrel includes a sidewall portion doped with a p-type dopant;
a first oxide pillar on a first side of the sacrificial mandrel and a second oxide pillar on the opposite side of the sacrificial mandrel, wherein the first oxide pillar has a width in the range of about 10 nm to about 60 nm, and the second oxide pillar has a width in the range of about 10 nm to about 30 nm, wherein the width of the second oxide pillar is less than the width of the first oxide pillar, and the first oxide pillar is in physical contact with the doped sidewall portion of the sacrificial mandrel; and
a capping layer covering a top surface of the sacrificial mandrel including the doped sidewall portion, at least a portion of the first oxide pillar, and at least a portion of the second oxide pillar.
2. The intermediate FinFET structure of claim 1 , wherein the sacrificial mandrel is amorphous silicon, and the first oxide pillar and second oxide pillar are silicon oxide.
3. The intermediate FinFET structure of claim 2 , wherein the first oxide pillar has a width in the range of about 15 nm to about 60 nm.
4. A plurality of semiconductor devices on a substrate, comprising:
at least ten fins on the substrate, wherein a first fin of the at least ten fins is separated from a directly adjacent second fin by a gap, G 2 , the second fin is separated from a directly adjacent third fin by a gap, G 4 , the third fin is separated from a directly adjacent fourth fin by a gap, G 1 , and the fourth fin is separated from a directly adjacent fifth fin by a gap, G 3 , wherein the gap, G 1 , is less than the gap, G 2 , and the gap, G 3 , is different from the gaps, G 1 and G 2 , and gap, G 4 , is different from gap, G 3 , and each fin is separated from the directly adjacent fin by a trench, wherein gaps G 2 , G 4 , G 1 , and G 3 , form an ordered repeating sequence of gaps that is repeated at least one more time.
5. The plurality of semiconductor devices on a substrate of claim 4 , wherein a dielectric material is formed in each of the trenches.
6. The plurality of semiconductor devices on a substrate of claim 4 , further comprising, a nitride column on each of the plurality of fins.