Selective removal of semiconductor fins
An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.
1. A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor fins on a substrate;
forming a material liner on physically exposed surfaces of said plurality of semiconductor fins and said substrate;
applying and patterning a photoresist layer over said material liner, wherein at least a semiconductor fin is positioned between a pair of sidewalls of said patterned photoresist layer;
implanting an implant material into a top portion of said material liner employing an angled implantation process, wherein a first sidewall portion of said material liner located on one side of said semiconductor fin and a top portion of said material liner are converted into a compound material portion, and said implant material is not implanted into a second sidewall portion of said material liner located on another side of semiconductor fin;
removing said compound material portion selective to remaining portions of said material liner that are not implanted with said implant material; and
converting at least a portion of said semiconductor fin into a dielectric material portion, wherein said remaining portions of said material liner laterally surrounds said dielectric material portion.
2. The method of claim 1 , wherein said converting at least said portion of said semiconductor fin into said dielectric material portion is performed by a thermal process.
3. The method of claim 1 , wherein said converting at least said portion of said semiconductor fin into said dielectric material portion is performed by a plasma process.
4. The method of claim 1 , wherein said converting at least said portion of said semiconductor fin into said dielectric material portion is performed by an oxidation process, and said dielectric material portion comprises a semiconductor oxide.
5. The method of claim 1 , wherein said converting at least said portion of said semiconductor fin into said dielectric material portion is performed by a nitridation process, and said dielectric material portion comprises a semiconductor nitride.
6. The method of claim 1 , wherein said converting at least said portion of said semiconductor fin into said dielectric material portion is performed by a combination of an oxidation process and a nitridation process, and said dielectric material portion comprises a semiconductor oxynitride.
7. The method of claim 1 , wherein said dielectric material portion has a greater width at an upper portion than at a lower portion.
8. The method of claim 1 , wherein said dielectric material portion is laterally confined at all sides at a lower portion, and laterally confined at three sides at an upper portion without any remaining portion of the material liner located on a fourth side.
9. The method of claim 1 , wherein said dielectric material has a topmost surface that protrudes above a horizontal plane including a topmost surface of each semiconductor fin.
10. The method of claim 1 , further comprising forming a shallow trench isolation layer on a portion of said material liner, wherein a top surface of said shallow trench isolation layer is located below a topmost surface of said dielectric material portion.
11. The method of claim 1 , further comprising:
forming a gate dielectric on surfaces of said plurality of semiconductor fins and surfaces of said dielectric material portion; and
forming a gate electrode on said gate dielectric.
12. The method of claim 1 , wherein said material liner is composed of a dielectric material, and said implant material is a noble metal atom.
13. The method of claim 1 , wherein said material liner is composed of a dielectric material, and said implant material is a semiconductor atom.
14. The method of claim 1 , wherein said material liner is composed of a semiconductor material, and said implant material is a compound semiconductor material.
15. The method of claim 1 , wherein said material liner is composed of a conductive material, and said implant material is a noble metal atom.
16. The method of claim 1 , wherein said material liner is composed of a conductive material, and said implant material is a semiconductor atom.
17. The method of claim 1 , wherein said compound material portion has a faster etch rate than the material liner.
18. The method of claim 1 , wherein said implanting is performed an angle from 5 degrees to 45 degrees.
19. The method of claim 1 , wherein an entirety of the semiconductor fin is converted into said dielectric material portion.
20. The method of claim 1 , further comprising etching at least a region of said remaining portion of said material liner selective to said plurality of semiconductor fins, and removing at least a portion of said dielectric material portion.