Structure and method to improve FAV RIE process margin and Electromigration
A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
1. A method of forming fully aligned vias in a semiconductor device, the method comprising:
forming a first level interconnect line embedded in a first interlevel dielectric (ILD);
recessing the first level interconnect line to form a recess in the first interlevel dielectric;
laterally etching the exposed upper portion of the first interlevel dielectric bordering the recess;
depositing a dielectric cap layer on the first level interconnect line and on the first interlevel dielectric;
depositing a second interlevel dielectric on the dielectric cap layer; and
forming a via opening to expose the first level interconnect line.
2. The method according to claim 1 , wherein forming the via opening leaves a portion of the dielectric cap layer bordering the via opening on at least two sidewalls of the first interlevel dielectric.
3. The method according to claim 1 , wherein forming the via opening comprises forming a lower via opening portion and an upper via opening portion, wherein the lower via opening portion is self-aligned to the first level interconnect line and wherein the upper via opening portion is wider than the lower via opening portion.
4. The method according to claim 1 , wherein forming the via opening comprises forming a lower via opening portion and an upper opening via portion, wherein the lower via opening portion is bordered on at least two sides by a portion of the dielectric cap layer, and wherein the upper via opening portion is wider than the lower via opening portion.
5. The method of claim 1 , further comprising depositing a selective cobalt cap on an exposed surface of the recessed first level interconnect line prior to depositing the dielectric cap layer.
6. The method of claim 5 , wherein laterally etching comprises using HF as an etchant.
7. The method of claim 1 , wherein forming the via opening involves etching the second interlevel dielectric selectively with respect to the dielectric cap layer.
8. The method of claim 1 , wherein forming the via opening involves etching the dielectric cap layer selectively with respect to the first interlevel dielectric.
9. A method of forming fully aligned vias in a semiconductor device, the method comprising:
forming a first level interconnect line embedded in a first interlevel dielectric (ILD);
selectively depositing a dielectric on the first interlevel dielectric;
laterally etching the selectively deposited dielectric;
depositing a dielectric cap layer on the first level interconnect line, on the first interlevel dielectric, and on the selectively deposited dielectric;
depositing a second interlevel dielectric on the dielectric cap layer; and
forming a via opening to expose the first level interconnect line.
10. The method according to claim 9 , wherein forming the via opening leaves a portion of the dielectric cap layer bordering the via opening on at least two sidewalls of the selectively deposited dielectric.
11. The method according to claim 9 , wherein forming the via opening comprises forming a lower via opening portion and an upper via opening portion, wherein the lower via opening portion is self-aligned to the first level interconnect line and wherein the upper via opening portion is wider than the lower via opening portion.
12. The method according to claim 9 , wherein forming the via opening comprises forming a lower via opening portion and an upper via opening portion, wherein the lower via opening portion is bordered on at least two sides by a portion of the dielectric cap layer, and wherein the upper via opening portion is wider than the lower via opening portion.
13. The method of claim 9 , wherein forming the via opening involves etching the second interlevel dielectric selectively with respect to the dielectric cap layer.
14. The method of claim 9 , wherein forming the via opening involves etching the dielectric cap layer selectively with respect to the selectively deposited dielectric.
15. A method of forming fully aligned vias in a semiconductor device, the method comprising:
forming a first level interconnect line embedded in a first interlevel dielectric (ILD);
recessing the first level interconnect line to form a recess in the first interlevel dielectric;
laterally etching the exposed upper portion of the first interlevel dielectric bordering the recess;
depositing a plurality of dielectric layers to fill the recess and form a second interlevel dielectric; and
forming a via opening to expose the first level interconnect line.
16. The method according to claim 15 , wherein forming the via opening comprises forming a lower via opening portion and an upper via opening portion, wherein the lower via opening portion is self-aligned to the first level interconnect line and wherein the upper via opening portion is wider than the lower via opening portion.
17. A method of forming fully aligned vias in a semiconductor device, the method comprising:
forming a first level interconnect line embedded in a first interlevel dielectric (ILD);
selectively depositing a dielectric on the first interlevel dielectric;
laterally etching the selectively deposited dielectric;
depositing a plurality of dielectric layers to form a second interlevel dielectric; and
forming a via opening to expose the first level interconnect line.
18. The method according to claim 17 , wherein forming the via opening comprises forming a lower via opening portion and an upper via opening portion, wherein the lower via opening portion is self-aligned to the first level interconnect line and wherein the upper via opening portion is wider than the lower via opening portion.