IP Library Granted Patent US 10,504,793
Granted Patent B2
US 10,504,793 · App. 15/903,167 · Granted Dec 10, 2019

Hybrid-channel nano-sheet FETs

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Quick Facts
Patent No.
US 10,504,793
App. No.
15/903,167
Granted
Dec 10, 2019
Kind
B2
Abstract

Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region. First source/drain regions are grown in the first device region from exposed ends of the layers of the first channel material. Second source/drain regions are grown in the second device region from exposed ends of the layers of the second channel material.

Claims (37)

1. A method of forming semiconductor devices:

forming first layer caps at ends of layers of first material in stacks of alternating layers of first material and second material;

forming second layer caps at ends of the layers of second material;

etching away the first layer caps in only a first device region;

etching away the second layer caps in only a second device region;

growing first source/drain regions in the first device region from exposed ends of the layers of the first material; and

growing second source/drain regions in the second device region from exposed ends of the layers of the second material.

2. The method of claim 1 , wherein the first material is silicon and wherein the second material is silicon germanium.

3. The method of claim 1 , wherein the first source/drain regions are n-type doped and wherein the second source/drain regions are p-type doped.

4. The method of claim 1 , further comprising forming dummy gate structures on the stacks of alternating layers of first material and second material in the first and second device regions.

5. The method of claim 4 , further comprising etching away material of the stacks of alternating layers of first material and second material in areas that are not covered by the dummy gate structures.

6. The method of claim 4 , further comprising etching away the dummy gate structures after growing the first and second source/drain regions.

7. The method of claim 6 , further comprising etching away the layers of second material in the first device region and etching away the layers of first material in the second device region.

8. The method of claim 7 , further comprising depositing a first work function metal layer around the layers of first material in the first device region and depositing a second work function metal layer around the layers of second material in the second device region.

9. The method of claim 1 , wherein forming the first layer caps comprises oxidizing exposed portions of the first material.

10. The method of claim 1 , wherein forming the second layer caps comprises laterally etching the layers of the second material to form recesses and depositing a dielectric fill in the recesses.

11. The method of claim 1 , wherein the first layer caps are formed only on the layers of first material and the second layer caps are formed only on the layers of second material.

12. A method of forming semiconductor devices:

forming first layer caps at ends of layers of first material in stacks of alternating layers of first material and second material by oxidizing exposed portions of the first material;

forming second layer caps at ends of the layers of second material;

etching away the first layer caps in a first device region;

etching away the second layer caps in a second device region;

growing first source/drain regions in the first device region from exposed ends of the layers of the first material; and

growing second source/drain regions in the second device region from exposed ends of the layers of the second material.

13. The method of claim 12 , further comprising forming dummy gate structures on the stacks of alternating layers of first material and second material in the first and second device regions.

14. The method of claim 13 , further comprising etching away the dummy gate structures after growing the first and second source/drain regions, etching away the layers of second material in the first device region, and etching away the layers of first material in the second device region.

15. The method of claim 12 , wherein forming the second layer caps comprises laterally etching the layers of the second material to form recesses and depositing a dielectric fill in the recesses.

16. A method of forming semiconductor devices:

forming first layer caps at ends of layers of first material in stacks of alternating layers of first material and second material;

forming second layer caps at ends of the layers of second material by laterally etching the layers of the second material to form recesses and depositing a dielectric fill in the recesses;

etching away the first layer caps in a first device region;

etching away the second layer caps in a second device region;

growing first source/drain regions in the first device region from exposed ends of the layers of the first material; and

growing second source/drain regions in the second device region from exposed ends of the layers of the second material.

17. The method of claim 16 , further comprising forming dummy gate structures on the stacks of alternating layers of first material and second material in the first and second device regions.

18. The method of claim 17 , further comprising etching away the dummy gate structures after growing the first and second source/drain regions, etching away the layers of second material in the first device region, and etching away the layers of first material in the second device region.

19. The method of claim 16 , wherein forming the first layer caps comprises oxidizing exposed portions of the first material.

Assignments (5)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0454 →
CHANGE OF NAME Recorded Mar 24, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 059498/0010 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2018
From: BI, ZHENXING; CHENG, KANGGUO; XU, PENG; XU, WENYU
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 045015/0141 →