IP Library Granted Patent US 10,593,643
Granted Patent B2
US 10,593,643 · App. 16/058,425 · Granted Mar 17, 2020

Package-on-package assembly with wire bonds to encapsulation surface

Inventors: Hiroaki Sato (Yokohama, JP); Teck-Gyu Kang (San Jose, CA); Belgacem Haba (Saratoga, CA); Philip R. Osborn (San Jose, CA); Wei-Shun Wang (Palo Alto, CA); Ellis Chau (San Jose, CA); Ilyas Mohammed (Santa Clara, CA); Norihito Masuda (Yokohama, JP); Kazuo Sakuma (Iwaki, JP); Kiyoaki Hashimoto (Kanagawa, JP); Kurosawa Inetaro (Kanagawa, JP); Tomoyuki Kikuchi (Kanagawa, JP)
Assignee: Tessera, Inc.
H01L24/48H01L23/13H01L23/3107H01L23/3128H01L23/4952H01L23/49811H01L24/73H01L25/043H01L25/0657H01L25/105H01L25/16H01L27/14618H01L27/14625H01L21/56H01L23/5389H01L24/16H01L24/45H01L24/49H01L2224/05599H01L2224/16145H01L2224/16225H01L2224/1713H01L2224/17179H01L2224/17181H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/45101H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/45155H01L2224/4824H01L2224/48091H01L2224/48106H01L2224/48145H01L2224/48227H01L2224/48245H01L2224/48247H01L2224/48455H01L2224/48464H01L2224/49105H01L2224/49171H01L2224/73204H01L2224/73207H01L2224/73215H01L2224/73253H01L2224/73265H01L2225/0651H01L2225/06506H01L2225/06513H01L2225/06517H01L2225/06565H01L2225/06568H01L2225/107H01L2225/1023H01L2225/1035H01L2225/1041H01L2225/1052H01L2225/1058H01L2924/00011H01L2924/00012H01L2924/00014H01L2924/014H01L2924/01049H01L2924/01087H01L2924/12042H01L2924/1431H01L2924/1434H01L2924/15311H01L2924/15331H01L2924/181H01L2924/1815H01L2924/18165H01L2924/19107
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Quick Facts
Patent No.
US 10,593,643
App. No.
16/058,425
Granted
Mar 17, 2020
Kind
B2
Abstract

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Claims (40)

1. A method for forming a microelectronic package, comprising:

obtaining a substrate having first contacts on an upper surface thereof;

attaching a microelectronic die having a lower surface to face the upper surface of the substrate, the microelectronic die having second contacts on an upper surface of the microelectronic die;

bonding wire bonds to the first contacts including forming bases of the wire bonds during the bonding, the wire bonds having edge surfaces between the bases and corresponding end surfaces;

wherein a first portion of the wire bonds is interconnected between a first portion of the first contacts and the second contacts;

wherein the end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die;

forming a dielectric layer above the upper surface of the substrate and between the wire bonds;

bending uppermost portions of the second portion of the wire bonds over to be parallel with an upper surface of the dielectric layer; and

forming a redistribution layer above and on the upper surface of the dielectric layer and interconnected to the end surfaces of the second portion of the first wire bonds for electrical conductivity.

2. The method according to claim 1 , wherein the uppermost portions have corresponding sections of the edge surfaces flush with the upper surface of the dielectric layer.

3. The method according to claim 1 , wherein the uppermost portions have corresponding sections of the edge surfaces above the upper surface of the dielectric layer.

4. A method for forming a microelectronic package, comprising:

obtaining a substrate having first contacts on an upper surface thereof;

attaching a microelectronic die having a lower surface to face the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die;

bonding wire bonds to the first contacts including forming bases of the wire bonds during the bonding on the first contacts, the wire bonds having edge surfaces between the bases and corresponding end surfaces, the edges surfaces of the wire bonds having bends between the bases and the end surfaces;

wherein a first portion of the wire bonds is interconnected between a first portion of the first contacts and the second contacts;

wherein the end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die;

forming a dielectric layer above the upper surface of the substrate and between the wire bonds; and

wherein an upper surface of the dielectric layer defines recesses around uppermost portions of the second portion of the wire bonds, the uppermost portions extending in the recesses corresponding thereto.

5. The method according to claim 4 , further comprising:

forming coatings respectively disposed around portions of the edge surfaces corresponding to the uppermost portions of the second portion of the wire bonds;

removing uppermost portions of the coatings; and

wherein the recesses are defined responsive to removal of the uppermost portions of coatings respectively disposed around portions of the edge surfaces of the second portion of the wire bonds.

6. The method according to claim 4 , further comprising forming a redistribution layer above and on the upper surface of the dielectric layer and interconnected to the end surfaces of the second portion of the first wire bonds for electrical conductivity.

7. A method for forming a microelectronic package, comprising:

obtaining a substrate having first contacts on an upper surface thereof and second contacts on a lower surface thereof, the substrate defining a hole therein;

attaching a microelectronic die having a lower surface to face the upper surface of the substrate, the microelectronic die having third contacts on the lower surface thereof and positioned over the hole for alignment with the third contacts;

bonding first wire bonds to the first contacts including forming bases of the first wire bonds during the bonding, the first wire bonds having edge surfaces between the bases and corresponding end surfaces;

bonding second wire bonds for interconnection between the second contacts and the third contacts; and

forming a dielectric layer above the upper surface of the substrate and between the first and the second wire bonds.

8. The method according to claim 7 , wherein the end surfaces of the first wire bonds are above the upper surface of the microelectronic die.

9. The method according to claim 8 , wherein an upper surface of the dielectric layer defines recesses around uppermost portions of the first wire bonds, the uppermost portions extending in the recesses corresponding thereto.

10. The method according to claim 7 , further comprising bending uppermost portions of the first wire bonds over to be parallel with an upper surface of the dielectric layer.

11. The method according to claim 7 , further comprising forming a redistribution layer above and on the upper surface of the dielectric layer and interconnected to the end surfaces of the first wire bonds for electrical conductivity.

12. The method according to claim 9 , further comprising:

forming coatings respectively disposed around portions of the edge surfaces corresponding to the uppermost portions of the first wire bonds;

removing uppermost portions of the coatings; and

wherein the recesses are defined responsive to removal of the uppermost portions of coatings respectively disposed around portions of the edge surfaces of the first wire bonds.

13. The method according to claim 10 , wherein the uppermost portions of the first wire bonds have corresponding sections of the edge surfaces flush with the upper surface of the dielectric layer.

14. The method according to claim 10 , wherein the uppermost portions of the first wire bonds have corresponding sections of the edge surfaces located above the upper surface of the dielectric layer.

Assignments (4)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0454 →
CERTIFICATE OF CONVERSION & CHANGE OF NAME Recorded Jun 27, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 060443/0792 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2018
From: SATO, HIROAKI; KANG, TECK-GYU; HABA, BELGACEM; OSBORN, PHILIP R.; WANG, WEI-SHUN; CHAU, ELLIS; MOHAMMED, ILYAS; MASUDA, NORIHITO; SAKUMA, KAZUO; HASHIMOTO, KIYOAKI; INETARO, KURASAWA; KIKUCHI, TOMOYUKI
To: TESSERA, INC.
Reel/Frame 046587/0466 →
Cited By (1)
US 12,635,591