FinFET gate cut after dummy gate removal
View Patent ↗Semiconductor devices and methods of forming the same include forming dummy gates over a semiconductor fin. An interlayer dielectric is formed around and between the dummy gates. The dummy gates are etched away, leaving gate voids. A first planarizing material is deposited in and over the gate voids. The first planarizing material is removed in a gate cut region. A gate cut plug is deposited in the gate cut region. The remaining first planarizing material is removed to expose the gate voids outside of the gate cut region. A gate stack is formed in the gate voids outside of the gate cut region.
1. A method of forming a semiconductor device, comprising:
forming a plurality of dummy gates over a semiconductor fin;
forming an interlayer dielectric around and between the dummy gates;
etching away the dummy gates, leaving gate voids;
depositing a first planarizing material in and over the gate voids;
removing the first planarizing material in a gate cut region;
depositing a gate cut plug in the gate cut region;
removing the remaining first planarizing material to expose the gate voids outside of the gate cut region;
forming a gate stack in the gate voids outside of the gate cut region.
2. The method of claim 1 , further comprising forming the semiconductor fins from a semiconductor substrate using sidewall image transfer.
3. The method of claim 1 , further comprising depositing a second planarizing material after depositing the gate cut plug to fill any remaining voids.
4. The method of claim 3 , further comprising anisotropically etching the first planarizing material, the gate cut plug, and the second planarizing material down to at least a height of the interlayer dielectric.
5. The method of claim 1 , wherein removing the first planarizing material in the gate cut region comprises anisotropically etching the first planarizing material in the gate cut region as defined by a photolithographic resist mask.
6. The method of claim 1 , wherein the first planarizing material is an organic planarizing material and wherein removing the remaining first planarizing material comprises aching away the first planarizing material.
7. The method of claim 1 , wherein forming the gate stack comprises conformally depositing a gate dielectric, a work function metal layer, and a gate conductor.
8. A method of forming a semiconductor device, comprising:
forming a plurality of dummy gates over a semiconductor fin;
forming an interlayer dielectric around and between the dummy gates;
etching away the dummy gates, leaving gate voids;
depositing a first planarizing material in and over the gate voids;
removing the first planarizing material in a gate cut region;
depositing a gate cut plug in the gate cut region;
depositing a second planarizing material to fill any voids remaining after depositing the gate cut plug;
anisotropically etching the first material, the gate cut plug, and the second planarizing material down to at least a height of the interlayer dielectric;
removing the remaining first planarizing material to expose the gate voids outside of the gate cut region;
forming a gate stack in the gate voids outside of the gate cut region by depositing a gate dielectric, a work function metal layer, and a gate conductor.
9. The method of claim 8 , further comprising forming the semiconductor fins from a semiconductor substrate using sidewall image transfer.
10. The method of claim 8 , wherein removing the first planarizing material in the gate cut region comprises anisotropically etching the first planarizing material in the gate cut region as defined by a photolithographic resist mask.
11. The method of claim 8 , wherein the first planarizing material is an organic planarizing material and wherein removing the remaining first planarizing material comprises aching away the first planarizing material.