IP Library Granted Patent US 9,653,289
Granted Patent B1
US 9,653,289 · App. 15/268,993 · Granted May 16, 2017

Fabrication of nano-sheet transistors with different threshold voltages

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Quick Facts
Patent No.
US 9,653,289
App. No.
15/268,993
Granted
May 16, 2017
Kind
B1
Abstract

A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.

Claims (24)

1. A method of forming two or more nano-sheet devices with varying electrical gate lengths, comprising:

forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate;

removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers; and

removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layer, where the recess depth is greater than the indentation depth.

2. The method of claim 1 , further comprising forming the plurality of sacrificial release layers and the at least one alternating nano-sheet channel layer on the substrate by an epitaxially growth process, patterning and etching the plurality of sacrificial release layers and the at least one alternating nano-sheet channel layer to form a channel stack, and forming a dummy gate on the channel stack.

3. The method of claim 2 , wherein the at least two cut-stacks are formed from the same channel stack.

4. The method of claim 1 , further comprising forming a mask on at least one of the at least two cut-stacks after removing a portion of the plurality of sacrificial release layers, and removing an additional portion of the plurality of sacrificial release layers from the unmasked cut-stacks.

5. The method of claim 4 , wherein the additional portion of the plurality of sacrificial release layers is removed using an isotropic wet etch.

6. The method of claim 1 , further comprising forming a mask on at least one of the at least two cut-stacks before removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the unmasked cut-stacks.

7. The method of claim 6 , further comprising removing the mask from the at least one of the at least two cut-stacks after removing a portion of the at least one alternating nano-sheet channel layer, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the previously masked at least one of the at least two cut-stacks and an additional portion of the at least one alternating nano-sheet channel layer from the unmasked at least one of the at least two cut-stacks.

8. The method of claim 7 , wherein the recess depth in the at least one of the at least two cut-stacks is greater than the recess depth in the other at least two cut-stacks.

9. The method of claim 1 , further comprising forming a source/drain on each of the at least two cut-stacks.

10. The method of claim 9 , wherein the source/drains are epitaxially grown on the exposed surfaces of the at least one alternating nano-sheet channel layer.

11. A method of forming two or more nano-sheet devices with varying electrical gate lengths, comprising:

forming a channel stack including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate;

forming two or more dummy gates including a dummy gate fill and a side spacer on the channel stack;

removing exposed portions of the channel stack not covered by the two or more dummy gates to form two or more cut-stacks;

removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers;

forming an indentation fill layer in the indentations;

forming a mask on at least one of the two or more cut-stacks; and

removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the unmasked cut-stacks.

12. The method of claim 11 , further comprising removing the mask from the at least one of the two or more cut-stacks after removing a portion of the at least one alternating nano-sheet channel layer, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the previously masked at least one of the two or more cut-stacks and an additional portion of the at least one alternating nano-sheet channel layer from the at least one unmasked of the two or more cut-stacks.

13. The method of claim 12 , further comprising forming a source/drain on each of the two or more cut-stacks.

14. The method of claim 13 , further comprising removing the dummy gate fill and forming a gate structure on each of the two or more cut-stacks.

Assignments (5)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0454 →
CHANGE OF NAME Recorded Mar 24, 2022
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 059498/0010 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 051493/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2016
From: BALAKRISHNAN, KARTHIK; CHENG, KANGGUO; HASHEMI, POUYA; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039780/0272 →