Self aligned replacement metal source/drain finFET

1. A method of forming a fin-shaped field effect transistor (finFET) device, the method comprising:

forming at least one fin that extends in a first direction;

covering the fin with a dummy gate stack that extends in a second direction perpendicular to the first direction and that divides the at least one fin into source and drain regions on opposing sides of the dummy gate stack;

covering the source and drain regions with an interlayer dielectric;

replacing the dummy gate stack with a replacement metal gate stack;

performing a first anneal at a first temperature after the replacement metal gate stack has replaced the dummy gate stack;

after performing the first anneal:

recessing a top portion of the interlayer dielectric; and

forming metallic source and drain regions.

2. The method of claim 1 , wherein the dummy gate stack includes a dummy gate dielectric under a dummy gate cap.

3. The method of claim 2 , further comprising:

forming spacers on sides of the dummy gate stack.

4. The method of claim 3 , wherein replacing the dummy gate stack with a replacement metal gate stack includes forming a high-K dielectric over the fin between the spacers.

5. The method of claim 4 , wherein replacing the dummy gate stack with a replacement metal gate stack includes:

depositing gate stack material over the fins; and

depositing a dielectric cap over the gate stack material.

6. The method of claim 1 , wherein the at least one fin is formed by an extension of a substrate that extends above an upper surface of a shallow trench isolation layer that is formed on top of the substrate.

7. The method of claim 6 , wherein the substrate is a bulk substrate.

8. The method of claim 6 , wherein the substrate is a silicon-on-isolator substrate.

9. The method of claim 6 , further comprising:

removing a portion of the shallow trench isolation layer between the spacers and outside of the dummy gate stack, before forming the high-k dielectric, to form a recessed gate.

10. The method of claim 1 , wherein the metallic source and drain regions are formed of one of: Nickel Silicide, Erbium Silicide, and Platinum Silicide, Cobalt Silicide, Titanium Silicide, Tungsten Silicide, Dysprosium Silicide, Yttrium Silicide, and Ytterbium Silicide.

11. The method of claim 1 , wherein recessing a top portion of the interlayer dielectric includes exposing a top portion of the source region.

12. The method of claim 1 , wherein recessing a top portion of the interlayer dielectric includes exposing a top portion of the drain region.

13. The method of claim 1 , wherein forming the metallic drain region includes:

recessing exposed fin regions;

depositing a first metal layer;

forming a metal silicide, removing unreacted first metal;

filling the remaining exposed opening with a second metal; and

planarizing the second metal.

14. The method of claim 13 , wherein dopants are ion implanted into said first metal layer after said first metal layer is deposited.

15. The method of claim 13 , wherein dopants are ion implanted into said exposed fin region before said first metal layer is deposited.

16. The method of claim 13 , wherein dopants are ion implanted into said metal silicide after forming said metal silicide, followed by a second anneal at a second temperature lower than said first temperature.

17. The method of claim 1 , wherein forming the metallic source region includes:

recessing exposed fin regions;

depositing a first metal layer;

forming a metal silicide, removing unreacted first metal;

filling the remaining exposed opening with a second metal; and

planarizing the second metal.