IP Library Granted Patent US 12,074,165
Granted Patent B2
US 12,074,165 · App. 18/231,187 · Granted Aug 27, 2024

Gate cut with integrated etch stop layer

Inventors: Marc A. Bergendahl (Troy, NY); Andrew M. Greene (Albany, NY); Rajasekhar Venigalla (Hopewell Junction, NY)
Assignee: Tessera LLC
H01L27/0886H01L21/02181H01L21/31144H01L21/32133H01L21/76802H01L21/76877H01L21/823431H01L21/823437H01L21/823468H01L21/823475H01L21/823821H01L23/5286H01L23/5329H01L23/62H01L27/0924H01L29/66545H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 12,074,165
App. No.
18/231,187
Granted
Aug 27, 2024
Kind
B2
Abstract

A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Claims (37)

1. A semiconductor structure comprising:

a first gate structure and a second gate structure in-line with one another and separated by a gate cut; and

a trench comprising a power rail, wherein:

the first and second gate structures extend in a first horizontal direction and each comprise a metal gate and a dielectric gate cap;

the trench and the power rail extend through the gate cut in a second horizontal direction perpendicular to the first horizontal direction; and

an upper surface of the dielectric gate cap of the first gate structure is substantially co-planar with an upper surface of the power rail.

2. The semiconductor structure of claim 1 , wherein an upper surface of the dielectric gate cap of the second gate structure is substantially co-planar with the upper surface of the power rail.

3. The semiconductor structure of claim 1 , further comprising a source contact region connected to the power rail.

4. The semiconductor structure of claim 1 , further comprising a dielectric layer disposed on sidewalls of the trench between the power rail and the first and second gate structures.

5. The semiconductor structure of claim 4 , wherein the dielectric layer comprises an oxide.

6. The semiconductor structure of claim 5 , wherein the dielectric layer comprises hafnium oxide.

7. The semiconductor structure of claim 1 , wherein the power rail comprises tungsten.

8. The semiconductor structure of claim 1 , wherein the power rail comprises cobalt.

9. The semiconductor structure of claim 1 , wherein the power rail comprises ruthenium.

10. The semiconductor structure of claim 1 , wherein the power rail comprises titanium, aluminum, or copper.

11. The semiconductor structure of claim 1 , wherein the first gate structure is disposed on a first fin structure and the second gate structure is disposed on a second fin structure.

12. The semiconductor structure of claim 1 , wherein:

the trench comprises an upper portion and a lower portion;

the upper portion substantially comprises the power rail; and

the lower portion substantially comprises one or more dielectric materials.

13. A semiconductor structure comprising:

a plurality of gate line structures each comprising a gate cut; and

a trench comprising a power rail, wherein:

the plurality of gate line structures extend in parallel in a first horizontal direction;

each of the plurality of gate line structures comprises a metal gate and a dielectric gate cap;

the trench and the power rail extend through the gate cut of each gate line structure in a second horizontal direction perpendicular to the first horizontal direction; and

upper surfaces of the dielectric gate caps of each gate line structure are substantially co-planar with an upper surface of the power rail.

14. The semiconductor structure of claim 13 , wherein each of the plurality of gate line structures comprises a first gate structure and a second gate structure in-line with one another and separated by the gate cut.

15. The semiconductor structure of claim 13 , further comprising plural source contact regions connected to the power rail.

16. The semiconductor structure of claim 13 , further comprising a dielectric layer disposed on sidewalls of the trench between the power rail and the plurality of gate line structures.

17. The semiconductor structure of claim 16 , wherein the dielectric layer comprises an oxide.

18. The semiconductor structure of claim 17 , wherein the dielectric layer comprises hafnium oxide.

19. The semiconductor structure of claim 18 , wherein the power rail comprises tungsten, cobalt, ruthenium, titanium, aluminum, or copper.

20. The semiconductor structure of claim 13 , wherein:

the trench comprises an upper portion and a lower portion;

the upper portion substantially comprises the power rail; and

the lower portion substantially comprises one or more dielectric materials.

Assignments (4)
CHANGE OF NAME Recorded Sep 27, 2024
From: TESSERA LLC
To: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 069067/0454 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2023
From: BERGENDAHL, MARC A.; GREENE, ANDREW M.; VENIGALLA, RAJASEKHAR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 064690/0785 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2023
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: TESSERA, INC.
Reel/Frame 064690/0824 →
CHANGE OF NAME Recorded Aug 24, 2023
From: TESSERA, INC.
To: TESSERA LLC
Reel/Frame 064691/0071 →
Continuity (6)
Continuation 18076755 · Dec 7, 2022
Continuation 17221401 · Apr 2, 2021
Continuation 16738569 · Jan 9, 2020
Continuation 16054394 · Aug 3, 2018
Continuation 15258513 · Sep 7, 2016
Related Publication 20240222373A1 · Jul 4, 2024