Air gap spacer formation for nano-scale semiconductor devices
Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.
1. A semiconductor integrated circuit device comprising:
a substrate;
a first interconnect level; and
a second interconnect level above the first interconnect level, the second interconnect level comprising:
a first metal line extending in a first direction parallel to the substrate;
a second metal line adjacent to and parallel to the first metal line and extending in the first direction;
an air gap spacer extending in the first direction between the first and second metal lines and extending vertically to a pinch-off region formed in a dielectric capping material, wherein the pinch-off region is formed above a plane comprising top surfaces of the first and second metal lines;
a first self-aligned conductive protective cap on the first metal line;
a second self-aligned conductive protective cap on the second metal line; and
a conformal insulating liner disposed directly on top of a conductive portion of the first and second self-aligned conductive protective caps and on opposing sides of the first and second metal lines adjacent the air gap spacer, the conformal insulating liner being continuous below the air gap spacer,
wherein a lateral distance between the first and second metal lines is in a range from 6 nm to 10 nm, and
wherein a thickness of the conformal insulating liner is in a range from 0.5 nm to less than 5 nm.
2. The semiconductor integrated circuit device of claim 1 , wherein the conformal insulating liner comprises a plurality of conformal layers.
3. The semiconductor integrated circuit device of claim 2 , wherein each of the plurality of conformal layers have thicknesses in a range between 0.1 nm and 0.2 nm.
4. The semiconductor integrated circuit device of claim 2 , wherein the plurality of conformal layers comprise SiN.
5. The semiconductor integrated circuit device of claim 1 , wherein the conformal insulating liner comprises SiCNO.
6. The semiconductor integrated circuit device of claim 1 , wherein the conformal insulating liner comprises SiCBN.
7. The semiconductor integrated circuit device of claim 1 , wherein the first and second self-aligned protective caps comprise Co.
8. The semiconductor integrated circuit device of claim 1 , wherein the air gap spacer wraps around an end of the first metal line.
9. The semiconductor integrated circuit device of claim 1 , wherein the air gap spacer extends beyond an end of the first metal line and beyond an end of the second metal line.
10. The semiconductor integrated circuit device of claim 1 , wherein:
the dielectric capping material is disposed above the air gap spacer and on both (i) vertical portions of the conformal insulating liner on opposing sides of the first and second metal lines and (ii) a horizontal portion of the conformal insulating liner below the air gap spacer; and
the dielectric capping material is formed with a level of conformality of 40% or less.
11. The semiconductor integrated circuit device of claim 10 , wherein the air gap spacer extends vertically above a plane comprising a top surface of the first self-aligned protective cap and a top surface of the second self-aligned protective cap.
12. The semiconductor integrated circuit device of claim 10 , wherein the air gap spacer extends vertically below a plane comprising a bottom surface of the first metal line and a bottom surface of the second metal line.
13. The semiconductor integrated circuit device of claim 10 , wherein the dielectric capping material comprises an ultra-low-k material.
14. The semiconductor integrated circuit device of claim 13 , wherein the ultra- low-k material comprises porous SiCOH.
15. A semiconductor integrated circuit device comprising:
a substrate;
a first interconnect level; and
a second interconnect level above the first interconnect level, the second interconnect level comprising:
a first metal line extending in a first direction parallel to the substrate;
a second metal line adjacent to and parallel to the first metal line and extending in the first direction;
an air gap spacer disposed between the first and second metal lines and extending in the first direction;
a first self-aligned conductive protective cap on the first metal line;
a second self-aligned conductive protective cap on the second metal line;
a conformal insulating liner disposed directly on top of a conductive portion of the first and second self-aligned conductive protective caps and on opposing sides of the first and second metal lines adjacent the air gap spacer, the conformal insulating liner being continuous below the air gap spacer; and
a dielectric capping material disposed above the air gap spacer and on both (i) vertical portions of the conformal insulating liner on opposing sides of the first and second metal lines and (ii) a horizontal portion of the conformal insulating liner below the air gap spacer, wherein:
the dielectric capping material is formed with a level of conformality of 40% or less;
the air gap spacer extends vertically to a pinch-off region in the dielectric capping material; and
the pinch-off region is formed above a plane comprising a top surface of the first self-aligned protective cap a top surface of the second self-aligned protective cap.
16. The semiconductor integrated circuit device of claim 15 , wherein a lateral distance between the first and second metal lines is in a range from 6 nm to 10 nm and a thickness of the conformal insulating liner is in a range from 0.5 nm to less than 5 nm.
17. The semiconductor integrated circuit device of claim 15 , wherein the conformal insulating liner comprises a plurality of conformal layers.
18. The semiconductor integrated circuit device of claim 17 , wherein each of the plurality of conformal layers have thicknesses in a range between 0.1 nm and 0.2 nm.
19. The semiconductor integrated circuit device of claim 17 , wherein the conformal layers of the plurality of conformal layers comprise SiN.
20. The semiconductor integrated circuit device of claim 15 , wherein the conformal insulating liner comprises SiCNO.
21. The semiconductor integrated circuit device of claim 15 , wherein the conformal insulating liner comprises SiCBN.
22. The semiconductor integrated circuit device of claim 15 , wherein the first and second self-aligned protective caps consist of Co.
23. The semiconductor integrated circuit device of claim 15 , wherein the air gap spacer wraps around an end of the first metal line.
24. The semiconductor integrated circuit device of claim 15 , wherein the air gap spacer extends beyond an end of the first metal line and beyond an end of the second metal line.
25. The semiconductor integrated circuit device of claim 15 , wherein the air gap spacer extends vertically below a plane comprising a bottom surface of the first metal line and a bottom surface of the second metal line.
26. The semiconductor integrated circuit device of claim 15 , wherein the dielectric capping material comprises an ultra-low-k material.
27. The semiconductor integrated circuit device of claim 26 , wherein the ultra-low-k material comprises porous SiCOH.