Air gap spacer for metal gates
A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.
1. A method for forming a transistor device comprising:
forming a sacrificial spacer having a base width greater than an upper surface width that is abutting a gate structure;
forming a contact abutting the sacrificial spacer on at least one of a source region and a drain region;
removing the sacrificial spacer; and
forming a single conformal dielectric material layer on sidewalls of the contact and the gate structure, wherein the single conformal dielectric material layer is present around a perimeter of an air gap, and portions of the single conformal dielectric material layer contact one another to form the air gap.
2. The method of claim 1 , wherein the sacrificial spacer is formed in a trench, and forming the trench comprises:
forming an interlayer dielectric layer;
forming said trench in said interlayer dielectric layer exposing sidewall spacers on adjacent gate structures of said at least one gate structure;
recessing said sidewall spacers to provide remnant spacer portions; and
recessing a vertical portion of a gate dielectric of said adjacent gate structures.
3. The method of claim 2 , wherein recessing said vertical portion of said gate dielectric of said adjacent gate structures recesses are formed between a remaining portion of the gate structure and at least one of the source region and the drain region.
4. The method of claim 2 , wherein the gate structure is present on a channel region portion of a fin structure.
5. The method of claim 2 , wherein the vertical portion of the gate dielectric is removed using isotropic etching.
6. The method of claim 2 , wherein a second spacer material is deposited by chemical vapor deposition on the sacrificial spacer.
7. The method of claim 6 , wherein the forming of the sacrificial spacer on the sidewalls of the trench and on the sidewall of the at least one gate structure comprises:
depositing a continuous dielectric material layer on vertical surfaces of the trench sidewall and horizontal surfaces at a base of the trench; and
anisotropically etching the continuous dielectric material to remove the continuous dielectric material from the horizontal surfaces of the trench and to reduce a width of the continuous dielectric material at an upper surface of the vertical surfaces of the trench to provide said sacrificial spacer having an upper surface with a width less than a base surface of the sacrificial spacer.
8. The method of claim 7 , wherein said removing the sacrificial spacer comprises annealing.
9. A method for forming a fin field effect transistor (FinFET) device comprising:
forming a sacrificial spacer;
forming a contact abutting the sacrificial spacer, the contact in electrical communication with at least one of a source region and a drain region;
removing the sacrificial spacer to provide an air gap opening; and
forming a dielectric material layer in the air gap opening exposed by removing the sacrificial spacer, wherein the dielectric material layer is present around a perimeter of the air gap opening, and portions of the dielectric material layer contact one another at a pinch off region to form an air gap filling.
10. The method of claim 9 , wherein the sacrificial spacer is formed in a trench, and forming the trenches comprises:
forming an interlayer dielectric layer; and
forming said trenches in said interlayer dielectric layer by etching.
11. The method of claim 10 , wherein forming the sacrificial spacer comprises conformally depositing a sacrificial material layer on sidewall and base portions of the trench.
12. The method of claim 11 , wherein forming the sacrificial spacer further comprises etching the sacrificial material layer to remove horizontal portions at a base of the trench, wherein vertical portions of the sacrificial material layer remain to provide the sacrificial spacer.
13. The method of claim 11 , wherein the sacrificial spacer has a base width greater than an upper surface.
14. The method of claim 10 , wherein said removing the sacrificial spacer comprises annealing.
15. A method for forming a transistor device comprising:
forming a sacrificial spacer on sidewalls of the gate structure, wherein the sacrificial spacer has a base width greater than an upper surface width;
forming a contact to at least one of the source region and the drain region, wherein the contact abuts the sacrificial spacer;
removing the sacrificial spacer; and
forming a dielectric material layer in the air gap opening, wherein the dielectric material layer is present around a perimeter of the air gap opening to form an air gap.
16. The method of claim 15 , wherein the sacrificial spacer is present in a trench, and forming the trench comprises:
forming an interlayer dielectric layer;
forming said trench in said interlayer dielectric layer exposing sidewall spacers on adjacent gate structures of said at least one gate structure;
recessing said sidewall spacers to provide remnant spacer portions; and
recessing a vertical portion of a gate dielectric of said adjacent gate structures.
17. The method of claim 16 , wherein recessing said vertical portion of said gate dielectric of said adjacent gate structures recesses are formed between a remaining portion of the gate structure and at least one of the source region and the drain region.
18. The method of claim 16 , wherein the gate structure is present on a channel region portion of a fin structure.
19. The method of claim 16 , wherein the vertical portion of the gate dielectric is removed using isotropic etching.
20. The method of claim 16 , wherein the second spacer material is deposited by chemical vapor deposition.