Air gap spacer for metal gates
A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.
1. A method of forming a semiconductor structure, the method comprising:
providing a gate structure comprising an upper portion above a fin, wherein the gate structure comprises:
a work function metal disposed on sidewalls of a metal gate to collectively define a conductive portion of the gate;
a high-k dielectric material disposed on the work function metal; and
a gate spacer, wherein portions of the gate spacer are disposed between the high-k dielectric material and a source/drain region;
recessing the gate spacer to expose regions of the high-k dielectric material in the upper portion of the gate structure; and
after recessing the gate spacer, selectively etching the exposed regions of the high-k dielectric material, wherein selectively etching comprises selectively etching a portion of the high-k dielectric material between the gate spacer and the work function metal to form a recess therebetween.
2. The method of claim 1 , wherein the gate structure comprises a lower portion disposed on portions of the fin.
3. The method of claim 2 , wherein, subsequent to recessing the gate spacer, a remaining portion of the gate spacer is disposed between the lower portion of the gate structure and the source/drain region.
4. The method of claim 1 , comprising: recessing the gate spacer to below a top surface of the source/drain region.
5. The method of claim 1 , further comprising: providing a dielectric gate cap disposed on the gate structure.
6. The method of claim 5 , wherein the dielectric gate cap comprises silicon nitride, silicon oxide, or silicon oxynitride.
7. The method of claim 1 , comprising: subsequent to etching the exposed regions of the high-k dielectric material, depositing a second dielectric material on a sidewall portion of the gate structure where the high-k dielectric material was etched.
8. The method of claim 7 , wherein the second dielectric material is a conformal layer of dielectric material.
9. The method of claim 7 , wherein the second dielectric material is at least one of materials selected from a group comprising an oxide, a nitride, or an oxynitride.
10. The method of claim 7 , wherein the second dielectric material is at least one of materials selected from a group comprising polystyrenes, polymethyl methacrylates, polynorbornenes, or polypropylene glycols.
11. The method of claim 7 , wherein the second dielectric material is further deposited on the source/drain region.
12. The method of claim 7 , comprising: etching the second dielectric material to form a second gate spacer adjacent to the gate structure.
13. The method of claim 12 , further comprising forming a metal contact above the source/drain region adjacent to the second gate spacer.
14. The method of claim 13 , further comprising forming an airgap between the metal contact and the gate structure.
15. The method of claim 14 , further comprises etching the second dielectric material comprising the second gate spacer.
16. The method of claim 15 , further comprising depositing a third dielectric material between the metal contact and the gate structure.
17. The method of claim 14 , wherein the airgap extends vertically above a top surface of the gate structure.
18. The method of claim 17 , wherein a top surface of the airgap is below a top surface of the metal contact.
19. The method of claim 17 , further comprising: providing a dielectric gate cap disposed on the gate structure, wherein:
a top surface of the airgap is below a top surface of the dielectric gate cap.
20. The method of claim 1 , wherein the high-k dielectric material comprises hafnium and oxygen.